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參數(shù)資料
| 型號： | CY62256V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 32K x 8 Static RAM(32K x 8 靜態(tài)RAM) |
| 中文描述： | 32K的× 8靜態(tài)RAM（32K的× 8靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 418K |
| 代理商： | CY62256V |
256K (32K x 8) Static RAM
CY62256V
Cypress Semiconductor Corporation
Document #: 38-05057 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 25, 2006
Features
High Speed
— 70 ns
Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
Low voltage range:
— 2.7V – 3.6V
Low active power and standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Available in a Pb-free and non Pb-free standard 28-pin
narrow SOIC, 28-pin TSOP-1 and 28-pin Reverse
TSOP-1 packages
Functional Description
[1]
The CY62256V family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and Tri-state drivers.
These devices have an automatic power-down feature,
reducing the power consumption by over 99% when
deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
COLUMN
DECODER
R
S
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
32K × 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
10
A
1
A
1
A
1
A
0
A
1
A
1
Logic Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| CY6264-55SNXC | 8K x 8 Static RAM |
| CY6264-55SNXI | 8K x 8 Static RAM |
| CY6264-70SNI | 8K x 8 Static RAM |
| CY6264-70SNXA | 8K x 8 Static RAM |
| CY6264-70SNXC | 8K x 8 Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62256V-70SNCT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62256V-70ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY62256VL-70SNC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 256K-Bit 32K x 8 70ns 28-Pin SNC 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62256VL-70SNCT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| CY62256VL-70ZI | 制造商:Cypress Semiconductor 功能描述: |
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