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參數資料
| 型號： | CY64146V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4M (256K x 16) Static RAM |
| 中文描述： | 4分（256K × 16）靜態RAM |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 234K |
| 代理商： | CY64146V |
4M (256K x 16) Static RAM
CY62146V MoBL
Cypress Semiconductor Corporation
Document #: 38-05159 Rev. *A
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised August 27, 2002
Features
Wide voltage range: 2.7V
–
3.6V
Ultra-low active, standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a standard 44-Pin TSOP Type II
(forward pinout) package
Functional Description
[1]
The CY62146V is a high-performance CMOS static RAM
organized as 256K words by 16 bits. These devices feature
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
(MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH). The input/output pins (I/O
through
I/O
15
) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
to I/O
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Note:
1.
For best practice recommendations, please refer to the Cypress application note
“
System Design Guidelines
”
on http://www.cypress.com.
Logic Block Diagram
256K
×
16
RAM Array
2048
×
2048
I/O
0
–
I/O
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
BLE
I/O
8
–
I/O
15
CE
WE
BHE
A
1
A
0
A
1
A
9
A
10
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