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參數資料
| 型號： | CY7B991-7 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Skew Clock Buffer |
| 中文描述： | 可編程偏移時鐘緩沖器 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 288K |
| 代理商： | CY7B991-7 |
Programmable Skew Clock Buffer
CY7B991
CY7B992
Cypress Semiconductor Corporation
Document #: 38-07138 Rev. **
3901 North First Street
San Jose
CA 95134
Revised September 26, 2001
408-943-2600
92
Features
All output pair skew <100 ps typical (250 max.)
3.75- to 80-MHz output operation
User-selectable output functions
—Selectable skew to 18 ns
—Inverted and non-inverted
—Operation at
1
2
and
1
4
input frequency
—Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input to output delay
50% duty-cycle outputs
Outputs drive 50
terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Compatible with a Pentium
-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50
while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to
±
6 time units from their nominal
“
zero
”
skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this
“
zero delay
”
capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to
±
12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Pentium is a trademark of Intel Corporation.
Logic Block Diagram
Pin Configuration
7B991
–
1
7B991
–
2
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
1
2
3
4
32
31 30
17
16
15
14
18 19
20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3
F
V
R
G
T
2
F
2
2
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
C
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3
3
C
V
C
V
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
PLCC/LCC
CY7B991
CY7B992
FILTER
PHASE
FREQ
DET
相關PDF資料 |
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|---|---|
| CY7B991 | Programmable Skew Clock Buffer |
| CY7B992-7LMB | Programmable Skew Clock Buffer |
| CY7B991-7LMB | Programmable Skew Clock Buffer |
| CY7B991-7JC | Programmable Skew Clock Buffer |
| CY7B991-7JI | Programmable Skew Clock Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7B9917JC | 制造商:CYPRESS 功能描述:New |
| CY7B991-7JC | 功能描述:鎖相環 - PLL 5V 80MHz 8 TLL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B991-7JCT | 制造商:Cypress Semiconductor 功能描述:Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC T/R |
| CY7B991-7JI | 功能描述:IC CLK BUFF SKEW 8OUT 32PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| CY7B991-7JIT | 制造商:Cypress Semiconductor 功能描述:Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC T/R |
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