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參數資料
| 型號： | CY7B9911-5JCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Programmable Skew Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數： | 1/13頁 |
| 文件大?。?/td> | 321K |
| 代理商： | CY7B9911-5JCT |
CY7B9911
RoboClock+
Programmable Skew Clock Buffer
Cypress Semiconductor Corporation
Document Number: 38-07209 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 20, 2007
Features
■
All output pair skew <100 ps typical (250 max)
■
3.75 to 100 MHz output operation
■
User selectable output functions
Selectable skew to 18 ns
Inverted and non-inverted
Operation at and input frequency
Operation at 2x and 4x input frequency (input as low as 3.75
MHz)
■
Zero input to output delay
■
50% duty cycle outputs
■
Outputs drive 50
Ω
terminated lines
■
Low operating current
■
32-pin PLCC/LCC package
■
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Functional Description
The CY7B9911 High Speed Programmable Skew Clock Buffer
(PSCB) offers user selectable control over system clock
functions. This multiple output clock driver provides the system
integrator with functions necessary to optimize the timing of high
performance computer systems. Each of the eight individual TTL
drivers, arranged in four pairs of user controllable outputs, can
drive terminated transmission lines with impedances as low as
50
Ω
. They deliver minimal and specified output skews and full
swing logic levels.
Each output is hardwired to one of nine delay or function config-
urations. Delay increments of 0.6 to 1.5 ns are determined by the
operating frequency with outputs able to skew up to ±6 time units
from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and trans-
mission line delay effects. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that is multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty enabling maximum system clock speed and
flexibility.
Logic Block Diagram
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
FILTER
PHASE
FREQ
DET
相關PDF資料 |
PDF描述 |
|---|---|
| CY7B9911-7JC | Programmable Skew Clock Buffer (PSCB) |
| CY7B9911V-5JCT | High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V-5JXC | High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V-5JXCT | High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V-7JCT | High Speed Low Voltage Programmable Skew Clock Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7B9911-7JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B9911V | 制造商:Cypress Semiconductor 功能描述: |
| CY7B9911V_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V5JC | 制造商:Cypress Semiconductor 功能描述: |
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