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參數資料
| 型號： | CY7B9911 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB |
| 中文描述： | 高速低電壓偏差可編程時鐘緩沖器呂，PSCB |
| 文件頁數： | 1/11頁 |
| 文件大小： | 223K |
| 代理商： | CY7B9911 |
High-Speed Low-Voltage Programmable Skew Clock Buffer
(LV-PSCB)
CY7B9911V
3.3V RoboClock+
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
December 1, 1999
408-943-2600
Features
All output pair skew <100 ps typical (250 max.)
3.75- to 110-MHz output operation
User-selectable output functions
—Selectable skew to 18 ns
—Inverted and non-inverted
—Operation at
1
2
and
1
4
input frequency
—Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input-to-output delay
50% duty-cycle outputs
LVTTL outputs drive 50
terminated lines
Operates from a single 3.3V supply
Low operating current
32-pin PLCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Functional Description
The CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage
Programmable Skew Clock Buffer (LVPSCB) offers user-
selectable control over system clock functions. These multiple-
output clock drivers provide the system integrator with func-
tions necessary to optimize the timing of high-performance
computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated
transmission lines with impedances as low as 50
while deliv-
ering minimal and specified output skews and full-swing logic levels
(LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to
±
6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission
line delay effects to be canceled. When this “zero delay” capa-
bility of the LVPSCB is combined with the selectable output
skew functions, the user can create output-to-output delays of
up to
±
12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Logic Block Diagram
Pin Configuration
7B9911V–1
7B9911V–2
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
1
2
3
4
32
31 30
17
16
15
14
18 19
20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3
F
V
R
G
T
2
F
2
2
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
C
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3
3
C
V
C
V
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
PLCC
CY7B9911V
FILTER
PHASE
FREQ
DET
相關PDF資料 |
PDF描述 |
|---|---|
| CY7B9911V | High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB |
| CY7B9911V-5JC | High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB |
| CY7B9911V-7JC | High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB |
| CY7B991V-2JC | Low Voltage Programmable Skew Clock Buffer |
| CY7B991V-5JC | Low Voltage Programmable Skew Clock Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7B9911_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B9911_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B99115JC | 制造商:CYPRESS 功能描述:* |
| CY7B9911-5JC | 功能描述:鎖相環 - PLL 5V,100MHz,8 TTL Out Programmable Skew RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9911-5JCT | 功能描述:鎖相環 - PLL 5V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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