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參數資料
| 型號： | CY7C1020V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 32K x 16 Static RAM(32K x 16 靜態 RAM) |
| 中文描述： | 32K的× 16靜態RAM（32K的× 16靜態RAM）的 |
| 文件頁數： | 1/13頁 |
| 文件大小： | 182K |
| 代理商： | CY7C1020V |
32K x 16 Static RAM
CY7C1020V
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 1996 - Revised April 13, 1998
Features
3.3V operation (3.0V - 3.6V)
High speed
—t
AA
= 10 ns
Low active power
—540 mW (max., 12 ns)
Very Low standby power
—330
μ
W (max., “L” version)
Automatic power-down when deselected
Independent Control of Upper and Lower bytes
Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020V is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
14
). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O
9
through I/O
16
) is written into the location speci-
fied on the address pins (A
0
through A
14
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
1
to I/O
8
. If byte high enable (BHE) is LOW, then
data from memory will appear on I/O
9
to I/O
16
. See the truth
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020V is available in standard 44-pin TSOP type II
and 400-mil-wide SOJ packages.
Selection Guide
7C1020V-10
10
130
100
1
0.1
7C1020V-12
12
120
90
1
0.1
7C1020V-15
15
110
80
1
0.1
7C1020V-20
20
100
70
1
0.1
Maximum Access Time (ns)
Maximum Operating Current (mA)
L
Maximum CMOS Standby Current (mA)
L
WE
A
10
A
9
A
8
A
7
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
5
I/O
6
NC
NC
A
14
A
13
A
12
A
11
OE
BHE
BLE
V
SS
V
CC
I/O
12
I/O
11
I/O
10
I/O
9
A
0
A
1
A
2
I/O
16
I/O
15
I/O
14
I/O
13
CE
I/O
1
I/O
2
I/O
3
I/O
4
NC
A
3
A
4
A
5
A
6
1020V-2
18
19
20
21
27
26
25
24
22
23
NC
I/O
7
I/O
8
32K x 16
RAM Array
I/O
1
– I/O
8
R
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
A
9
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
BLE
I/O
9
– I/O
16
OE
WE
A
8
A
7
1020V-1
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