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參數資料
| 型號： | CY7C1021 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 16 Static RAM(64K x 16 靜態 RAM) |
| 中文描述： | 64K的× 16靜態RAM（64K的× 16靜態RAM）的 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 244K |
| 代理商： | CY7C1021 |
64K x 16 Static RAM
CY7C1021
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 18, 1998
Features
High speed
—t
AA
= 12 ns
CMOS for optimum speed/power
Low active power
—1320 mW (max.)
Automatic power-down when deselected
Independent Control of Upper and Lower bits
Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1021 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O
9
through I/O
16
) is written into the location speci-
fied on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
1
to I/O
8
. If byte high enable (BHE) is LOW, then
data from memory will appear on I/O
9
to I/O
16
. See the truth
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021 is available in standard 44-pin TSOP Type II
and 400-mil-wide SOJ packages.
WE
A
15
A
14
A
13
A
NC
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
5
I/O
6
A
4
A
3
A
2
A
1
A
0
OE
BHE
BLE
V
SS
V
CC
I/O
12
I/O
11
I/O
10
I/O
9
A
5
A
6
A
7
I/O
16
I/O
15
I/O
14
I/O
13
CE
I/O
1
I/O
2
I/O
3
I/O
4
NC
A
8
A
9
A
10
A
11
1021-2
18
19
20
21
27
26
25
24
22
23
NC
I/O
7
I/O
8
64K x 16
RAM Array
512 X 2048
I/O
1
– I/O
8
R
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
A
9
A
1
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
BLE
I/O
9
– I/O
16
OE
WE
A
8
Selection Guide
7C1021-10
10
220
5
0.5
7C1021-12
12
220
5
0.5
7C1021-15
15
220
10
0.5
7C1021-20
20
220
10
0.5
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
Commercial
L
Shaded areas contain advanced information.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C102112VC | 制造商:CYPRESS 功能描述:* |
| CY7C1021-12VC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1021-12VCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 1M-Bit 64K x 16 12ns 44-Pin SOJ T/R |
| CY7C1021-12ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1021-15VC | 制造商:Cypress Semiconductor 功能描述: |
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