
512K x 8 Static RAM
CY7C1049B
Cypress Semiconductor Corporation
Document #: 38-05169 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised September 13, 2002
408-943-2600
049B
Features
High speed
—t
AA
= 12 ns
Low active power
—1320 mW (max.)
Low CMOS standby power (Commercial L version)
—2.75 mW (max.)
2.0V Data Retention (400
μ
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
[1]
The CY7C1049B is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Logic Block Diagram
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049B is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Pin Configuration
Note:
1.
For guidelines on SRAM system design, please refer to the
‘
System Design Guidelines
’
Cypress application note, available on the internet at www.cypress.com.
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
CE
A
1
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
23
22
24
28
27
26
25
29
32
31
30
Top View
SOJ
33
36
35
34
16
17
21
20
GND
I/O
2
I/O3
A
1
A
2
A
3
A
4
CE
A
5
A
6
A
7
A
8
A
9
WE
V
CC
I/O
5
I/O
4
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
14
A
13
A
0
I/O
0
I/O
1
V
CC
A
1
18
19
GND
A
10
NC
NC
Selection Guide
7C1049B-12 7C1049B-15 7C1049B-17 7C1049B-20
12
15
240
220
8
8
-
-
-
-
7C1049B-25
25
180
8
0.5
9
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
17
195
8
0.5
-
20
185
8
0.5
9
Com
’
l
Com
’
l/Ind
’
l L
Ind
’
l