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參數資料
| 型號： | CY7C1223H-133AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mbit (128K x 18) Pipelined DCD Sync SRAM |
| 中文描述： | 128K X 18 CACHE SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 689K |
| 代理商： | CY7C1223H-133AXC |
2-Mbit (128K x 18) Pipelined DCD Sync SRAM
CY7C1223H
Cypress Semiconductor Corporation
Document #: 38-05674 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 6, 2006
Features
Registered inputs and outputs for pipelined operation
Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
128K × 18-bit common I/O architecture
3.3V core power supply
3.3V/2.5V I/O supply
Fast clock-to-output time
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous Output Enable
Offered in JEDEC-standard lead-free 100-pin TQFP
package
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1223H SRAM integrates 128K x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1223H operates from a +3.3V core power supply
while all outputs operate with either a +3.3V/2.5V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
166 MHz
3.5
240
40
133 MHz
4.0
225
40
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
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| CY7C1223H-166AXI | 2-Mbit (128K x 18) Pipelined DCD Sync SRAM |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C1223H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 2MBIT 128KX16 3.5NS 100TQFP - Bulk |
| CY7C1231H-133AXC | 功能描述:靜態隨機存取存儲器 128KX18 NoBL FT 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C123-7VC | 制造商:Cypress Semiconductor 功能描述:Static RAM, 256x4, 24 Pin, Plastic, SOJ |
| CY7C1243KV18-400BZC | 功能描述:靜態隨機存取存儲器 36MB (2Mx18) 1.8v 400MHz QDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1243KV18-450BZC | 功能描述:靜態隨機存取存儲器 36MB (2Mx18) 1.8v 450MHz QDR II 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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