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參數(shù)資料
| 型號： | CY7C1347F |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| 中文描述： | 4兆位（128K的× 36）流水線同步靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大小： | 423K |
| 代理商： | CY7C1347F |
4-Mbit (128K x 36) Pipelined Sync SRAM
Functional Description
[1]
The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic.
CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V
level, the I/O pins are 3.3V tolerant when V
DDQ
= 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 2.6 ns (250-MHz
device)
CY7C1347F supports either the interleaved burst sequence
used by the Intel Pentium processor or a linear burst sequence
used by processors such as the PowerPC
. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Address Strobe from
Processor (ADSP) or the Address Strobe from Controller
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the four Byte Write
Select (BW
[A:D]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a read cycle when emerging from a deselected
state.
CY7C1347F
Cypress Semiconductor Corporation
Document #: 38-05213 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 9, 2004
Features
Fully registered inputs and outputs for pipelined oper-
ation
128K by 36 common I/O architecture
3.3V core power supply
2.5V/3.3V I/O operation
Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100-pin TQFP, 119-pin BGA and
165-pin fBGA packages
“ZZ” Sleep Mode option and Stop Clock option
Available in Industrial and Commercial temperature
ranges
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Logic Block Diagram
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW
B
BW
C
BW
D
BW
A
ARRAY
DQs
DQP
A
DQP
B
DQP
C
DQP
D
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
D
,DQP
D
BYTE
WRITE DRIVER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1347F-133AC | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| CY7C1347F-133AI | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| CY7C1347F-133BGC | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| CY7C1347F-133BGI | 4-Mbit (128K x 36) Pipelined Sync SRAM |
| CY7C1347F-225BGC | 4-Mbit (128K x 36) Pipelined Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1347F-100AC | 功能描述:IC SRAM 4.5MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1347F-133AC | 功能描述:IC SRAM 4.5MBIT 133MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1347F-133BGI | 制造商:Rochester Electronics LLC 功能描述:4M- 128KX36 3.3V PIPELINE 1CD STD. SPEED-SYNCHRONOUS SRAM - Bulk |
| CY7C1347F-166BGCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1347F-166BGI | 制造商:Cypress Semiconductor 功能描述: |
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