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參數(shù)資料
| 型號(hào)： | CY7C1351-40AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128Kx36 Flow-Through SRAM with NoBL TM Architecture |
| 中文描述： | 128K X 36 ZBT SRAM, 14 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大小： | 195K |
| 代理商： | CY7C1351-40AC |
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128Kx36 Flow-Through SRAM with NoBL Architecture
Functional Description
CY7C1351
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 9, 1999
Features
Pin compatible and functionally equivalent to ZBT de-
vices IDT71V547, MT55L128L36F, and MCM63Z737
Supports 66-MHz bus operations with zero wait states
—Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for Flow-Through operation
Byte Write capability
128K x 36 common I/O architecture
Single 3.3V power supply
Fast clock-to-output times
—11.0 ns (for 66-MHz device)
—12.0 ns (for 50-MHz device)
—14.0 ns (for 40-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100 TQFP package
Burst Capability—linear or interleaved burst order
Low standby power
The CY7C1351 is a 3.3V, 128K by 36 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351 is equipped with the
advanced No Bus Latency (NoBL) logic required to en-
able consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in sys-
tems that require frequent Write/Read transitions. The
CY7C1351 is pin/functionally compatible to ZBT SRAMs
IDT71V547, MT55L128L36F, and MCM63Z737.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 11.0 ns (66-MHz
device).
Write operations are controlled by the four Byte Write Select
(BWS
[3:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
.
CLK
A
[16:0]
CEN
CE
1
CE
2
WE
[3:0]
Mode
BWS
CE
3
OE
128KX36
MEMORY
ARRAY
Logic Block Diagram
DQ
[31:0]
DP
[3:0]
DD
Q
36
CE
CONTROL
and WRITE
LOGIC
ADV/LD
36
36
17
17
Selection Guide
7C1351-66
7C1351-50
7C1351-40
Maximum Access Time (ns)
11.0
12.0
14.0
Maximum Operating Current (mA)
Commercial
250 mA
200 mA
175 mA
Maximum CMOS Standby Current (mA)
Commercial
5 mA
5 mA
5 mA
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
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