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參數資料
| 型號： | CY7C1383D-133BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 1M X 18 CACHE SRAM, 6.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, BGA-119 |
| 文件頁數： | 1/29頁 |
| 文件大小： | 477K |
| 代理商： | CY7C1383D-133BGC |
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PRELIMINARY
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D
CY7C1383D
Cypress Semiconductor Corporation
Document #: 38-05544 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised November 2, 2004
Features
Supports 133-MHz bus operations
512K × 36/1M × 18 common I/O
3.3V –5% and +10% core power supply (V
DD
)
2.5V or 3.3V I/O supply (V
DDQ
)
Fast clock-to-output time
— 6.5 ns (133-MHz version)
— 8.5 ns (100-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Offered in JEDEC-standard lead-free 100-pin TQFP
,119-ball BGA and 165-ball fBGA packages
JTAG boundary scan for BGA and fBGA packages
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit
x 18 Synchronous Flow-through SRAMs, respectively
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
3[2]
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
x
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
The CY7C1381D/CY7C1383D allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1381D/CY7C1383D operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3,
CE
2
are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
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| CY7C1383F-133BZI | 功能描述:靜態隨機存取存儲器 18Mb (1Mb x 18) 靜態隨機存取存儲器 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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| CY7C1384D-166AXI | 功能描述:靜態隨機存取存儲器 18Mbit Pipeline 靜態隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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