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參數(shù)資料
| 型號(hào)： | CY7C1399V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 32K x 8 3.0V Static RAM(3.0V 32K x 8 靜態(tài) RAM) |
| 中文描述： | 32K的× 8 3.0V靜態(tài)RAM（3.0V 32K的× 8靜態(tài)RAM）的 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 171K |
| 代理商： | CY7C1399V |
32K x 8 3.0V Static RAM
CY7C1399V
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
January 1996 - Revised June 1996
408-943-2600
Features
Single 3.0V power supply
Ideal for low-voltage cache memory applications
High speed
—12/15 ns
Low active power
—198 mW (max.)
Low CMOS standby power (L)
—165
μ
W (max.), f=f
MAX
2.0V data retention (L)
—40
μ
W (max.)
Low-power alpha immune 6T cell
Plastic SOJ and TSOP packaging
Functional Description
The CY7C1399V is a high-performance 3.0V CMOS static
RAM organized as 32,768 words by 8 bits. Easy memory ex-
pansion is provided by an active LOW chip enable (CE) and
active LOW output enable (OE) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. The CY7C1399V is available in standard
300-mil-wide SOJ and 28-pin TSOP type I packages.
Selection Guide
7C1399V
12
12
60
500
50
7C1399V
15
15
55
500
50
7C1399V
20
20
50
500
50
7C1399V
25
25
45
500
50
7C1399V
35
35
40
500
50
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (
μ
A)
Maximum CMOS Standby Current (
μ
A)
L
Shaded area contains advanced information.
Logic Block Diagram
Pin Configurations
C1399V-1
C1399V-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
WE
A
4
A
3
A
2
A
1
OE
A
0
V
CC
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
5
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
32Kx 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
A
1
A
1
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