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參數資料
| 型號： | CY7C1486V25-200BGXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 中文描述： | 1M X 72 CACHE SRAM, 3 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1.76 MM HEIGHT, LEAD FREE, FBGA-209 |
| 文件頁數： | 1/32頁 |
| 文件大小： | 1021K |
| 代理商： | CY7C1486V25-200BGXI |
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72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
CY7C1480V25
CY7C1482V25
CY7C1486V25
Cypress Semiconductor Corporation
Document #: 38-05282 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 23, 2007
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
2.5V core power supply
2.5V/1.8V IO operation
Fast clock-to-output time
— 3.0 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1480V25, CY7C1482V25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1486V25
available in Pb-free and non-Pb-free 209-ball FBGA
package
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1480V25/CY7C1482V25/CY7C1486V25 SRAM
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and
CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
X
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) is active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see
“Pin Definitions” on page 7
and
“Truth
Table” on page 10
for further details). Write cycles can be one
to two or four bytes wide, as controlled by the byte write control
inputs. When it is active LOW, GW causes all bytes to be
written.
The CY7C1480V25/CY7C1482V25/CY7C1486V25 operates
from a +2.5V core power supply while all outputs may operate
with either a +2.5 or +1.8V supply. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.
Note
1. For best practices recommendations, refer to the Cypress application note
System Design Guidelines
at
www.cypress.com
.
Selection Guide
250 MHz
3.0
450
120
200 MHz
3.0
450
120
167 MHz
3.4
400
120
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1480V25 | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1486V25-250BGC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C148 | 1K x 4 Static RAM |
| CY7C150-15DMB | 1Kx4 Static RAM |
| CY7C150-15SC | 1Kx4 Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C149 WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C149-45PC | 功能描述:1KX4 18-PIN SRAM RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C150-10DC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CY7C15025PC | 制造商:CYPRESS 功能描述:* |
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