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參數資料
| 型號： | CY7C150-12SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 1Kx4 Static RAM |
| 中文描述： | 1K X 4 CACHE SRAM, 12 ns, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 238K |
| 代理商： | CY7C150-12SC |
1Kx4 Static RAM
CY7C150
Cypress Semiconductor Corporation
Document #: 38-05024 Rev. **
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised August 24, 2001
50
Features
Memory reset function
1024 x 4 static RAM for control store in high-speed com-
puters
CMOS for optimum speed/power
High speed
—10 ns (commercial)
—12 ns (military)
Low power
—495 mW (commercial)
—550 mW (military)
Separate inputs and outputs
5-volt power supply
±
10% tolerance in both commercial
and military
Capable of withstanding greater than 2001V static dis-
charge
TTL-compatible inputs and outputs
Functional Description
The CY7C150 is a high-performance CMOS static RAM de-
signed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory re-
set feature that allows the entire memory to be reset in two
memory cycles.
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any giv-
en time.
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D
0
D
3
) is written into the memory location
specified on the address pins (A
0
through A
9
).
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O
0
through O
3
).
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
PinConfiguration
C150
–
1
64x64
ARRA
A
0
A
1
A
2
A
3
A
4
A
5
COLUMNDECODER
R
S
DATAINPUT
CONTROL
O
0
O
1
O
2
O
3
A
6
A
7
A
8
D
0
D
1
D
2
D
3
OE
WE
CS
RS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
19
22
21
20
Top View
DIP/SOIC
7C150
A3
A4
A5
A6
A7
A8
A9
D0
D1
O2
VCC
A2
A1
A0
RS
WE
OE
D3
CS
O3
D2
C150-2
O0
O1
GND
23
24
A
9
Selection Guide
7C150
10
10
7C150
12
12
12
90
100
7C150
15
15
15
90
100
7C150
25
25
25
90
100
7C150
35
Maximum Access Time (ns)
Commercial
Military
Commercial
Military
35
90
100
Maximum Operating Current (mA)
90
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