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參數資料
| 型號： | CY7C1511V18-250BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
| 中文描述： | 8M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數： | 1/23頁 |
| 文件大?。?/td> | 374K |
| 代理商： | CY7C1511V18-250BZC |
PRELIMINARY
72-Mbit QDR-II SRAM 4-Word Burst
Architecture
CY7C1513V18
CY7C1515V18
CY7C1526V18
CY7C1511V18
Cypress Semiconductor Corporation
Document #: 38-05363 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised August 11, 2004
Features
Separate Independent Read and Write Data Ports
— Supports concurrent transactions
250-MHz Clock for High Bandwidth
4-Word Burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 500 MHz) at 250 MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two output clocks (C and C) accounts for clock skew
and flight time mismatching
Echo clocks (CQ and CQ) simplify data capture in high
speed systems
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
Available in ×8,x9, ×18, and ×36 configurations
Full data coherency providing most current data
Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)
15 × 17 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball
(11 × 15 matrix)
Variable drive HSTL output buffers
JTAG 1149.1 Compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1511V18–8M x 8
CY7C1526V18–8M x 9
CY7C1513V18–4M x 18
CY7C1515V18–2M x 36
Functional Description
The CY7C1511V18, CY7C1526V18, CY7C1513V18, and
CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR-II Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 8-bit words (CY7C1511V18) or 9-bit
words (CY7C1526V18) or 18-bit words (CY7C1513V18) or
36-bit words (CY7C1515V18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K and
K and C and C), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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| CY7C1513V18 | 72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
| CY7C1513V18-167BZC | 72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
| CY7C1513V18-200BZC | 72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
| CY7C1513V18-250BZC | 72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
| CY7C1515V18 | 72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
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