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參數資料
| 型號： | CY7C182-25PC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 09V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 8K X 9 CACHE SRAM, 25 ns, PDIP28 |
| 封裝： | 0.300 INCH, DIP-28 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 142K |
| 代理商： | CY7C182-25PC |
8Kx9 Static RAM
CY7C182
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
October 4, 1999
Features
High speed
—t
AA
= 25 ns
x9 organization is ideal for cache memory applications
CMOS for optimum speed/power
Low active power
—770 mW
Low standby power
—195 mW
TTL-compatible inputs and outputs
Automatic power-down when deselected
Easy memory expansion with CE
1
, CE
2
,
OE options
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bits and it is manufactured using Cypress’s high-
performance CMOS technology. Access times as fast as 25 ns
are available with maximum power consumption of only 770
mW.
The CY7C182, which is oriented toward cache memory appli-
cations, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
an active-LOW Chip Enable (CE
1
), an active HIGH Chip En-
able (CE
2
), an active-LOW Output Enable (OE), and three-
state drivers.
An active-LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
1
and WE in-
puts are both LOW, data on the nine data input/output pins
(I/O
0
through I/O
8
) is written into the memory location ad-
dressed by the address present on the address pins (A
0
through A
12
). Reading the device is accomplished by selecting
the device and enabling the outputs, (CE
1
and OE active LOW
and CE
2
active HIGH), while (WE) remains inactive or HIGH.
Under these conditions, the contents of the location addressed
by the information on address pins is present on the nine data
input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
PinConfiguration
C182–1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
0
A
1
A
9
A
1
A
1
I/O
0
C182–2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
I/O
3
GND
256 x 32 x 9
ARRAY
INPUT BUFFER
COLUMN
DECODER
R
S
POWER
DOWN
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
CE
2
WE
OE
Top View
DIP/SOJ
I/O
8
Selection Guide
7C182-25
7C182-35
7C182-45
Maximum Access Time (ns)
25
35
45
Maximum Operating Current (mA)
140
140
140
Maximum Standby Current (mA)
35
35
35
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C185-25ZC | 8K x 8 Static RAM |
| CY7C185-15SC | 8K x 8 Static RAM |
| CY7C185-15VI | 8K x 8 Static RAM |
| CY7C185-20SC | 8K x 8 Static RAM |
| CY7C185-20VI | 8K x 8 Static RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C182-25VC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 72K-Bit 8K x 9-Bit 25ns 28-Pin SOJ |
| CY7C182-25VCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 72K-Bit 8K x 9-Bit 25ns 28-Pin SOJ T/R |
| CY7C182-35SC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C182-35VC | 制造商:Cypress Semiconductor 功能描述: 制造商:Cypress Semiconductor 功能描述:Static RAM, 8Kx9, 28 Pin, Plastic, SOJ |
| CY7C18245PC | 制造商:CYP 功能描述:* |
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