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參數(shù)資料
| 型號： | CY7C235A-40PC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Ear Plug (500 pr/bg-4/cs) Bulk Packed for dispenser RoHS Compliant: NA |
| 中文描述： | 1K X 8 OTPROM, 20 ns, PDIP24 |
| 封裝： | 0.300 INCH, DIP-24 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 211K |
| 代理商： | CY7C235A-40PC |
1K x 8 Registered PROM
CY7C235A
Cypress Semiconductor Corporation
Document #: 38-04002 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 27, 2002
408-943-2600
1CY7C235A
Features
CMOS for optimum speed/power
High speed
—25 ns address set-up
—12 ns clock to output
Low power
—495 mW (Commercial)
—660 mW (Military)
Synchronous and asynchronous output enables
On-chip edge-triggered registers
Programmable asynchronous registers (INIT)
EPROM technology, 100% programmable
Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin
LCC and PLCC
5V
±
10% V
CC
, commercial and military
TTL-compatible I/O
Direct replacement for bipolar PROMs
Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C235A is a high-performance 1024-word by 8-bit
electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip
carrier, or 28-pin plastic leaded chip carrier. The memory cells
utilize proven EPROM floating gate technology and byte-wide
intelligent programming algorithms.
The CY7C235A replaces bipolar devices pin for pin and offers
the advantages of lower power, superior performance, and
high programming yield. The EPROM cell requires only 12.5V
for the supervoltage, and low current requirements allow for
gang programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that the
product will meet AC specification limits after customer
programming.
1
2
3
4
5
6
7
8
9
10
11
12
16
15
17
18
19
20
24
23
22
21
13
14
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
8
A
9
E
INIT
E
S
CP
O
7
O
6
O
5
O
4
O
3
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
PROGRAMMABLE
ARRAY
MULTIPLEXER
COLUMN
ADDROW
8-BIT
TRIGGERED
REGISTER
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
CP
CP
E
S
E
28
4
5
6
7
8
9
10
1112
3 2 1
27
1314151617
26
25
24
23
22
21
20
19
A
VC
G
A
A
O
O
O
0
18
O
O
NC
A
0
A
4
A
3
A
2
A
1
E
INIT
E
S
CP
NC
O
7
O
6
N
N
O
A
A
9
INIT
I
P
A
DIP
Top View
LCC/PLCC
Top View
ADDRESS
DECODER
Logic Block Diagram
Pin Configuration
Selection Guide
7C235A-25
25
12
90
7C235A-30
30
15
90
7C235A-40
40
20
90
120
Unit
ns
ns
mA
mA
Minimum Address Set-Up Time
Maximum Clock to Output
Maximum Operating
Current
Commercial
Military
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