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參數(shù)資料
| 型號： | CY7C372I |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | UltraLogic 64-Macrocell Flash CPLD |
| 中文描述： | UltraLogic 64宏單元CPLD的閃光 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 176K |
| 代理商： | CY7C372I |
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UltraLogic 64-Macrocell Flash CPLD
CY7C372i
Cypress Semiconductor Corporation
Document #: 38-03033 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 16, 2004
Features
64 macrocells in four logic blocks
32 I/O pins
Five dedicated inputs including two clock pins
In-System Reprogrammable (ISR) Flash technology
— JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
— f
MAX
= 125 MHz
— t
PD
= 10 ns
— t
S
= 5.5 ns
— t
CO
= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 44-pin PLCC, TQFP, and CLCC packages
Pin-compatible with the CY7C371i
Functional Description
The CY7C372i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C372i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic F
LASH
370i devices, the CY7C372i
is electrically erasable and ISR, which simplifies both design
and manufacturing flows, thereby reducing costs. The
Cypress ISR function is implemented through a JTAG serial
interface. Data is shifted in and out through the SDI and SDO
pins. The ISR interface is enabled using the programming
voltage pin (ISR
EN
). Additionally, because of the superior
routability of the F
LASH
370i devices, ISR often allows users to
change existing logic designs while simultaneously fixing
pinout assignments.
The 64 macrocells in the CY7C372i are divided between four
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Logic Block Diagram
PIM
INPUT
MACROCELLS
CLOCK
INPUTS
INPUTS
LOGIC
BLOCK
B
LOGIC
BLOCK
C
2
2
36
16
16
36
8 I/Os
8 I/Os
16
16
LOGIC
BLOCK
D
36
16
16
36
8 I/Os
8 I/Os
2
3
INPUT/CLOCK
MACROCELLS
I/O
0
-I/O
7
LOGIC
BLOCK
A
I/O
8
-I/O
15
I/O
16
-I/O
23
I/O
24
-I/O
31
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C372I-100JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 44-Pin PLCC 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 44-Pin PLCC |
| CY7C372I-125JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 44-Pin PLCC 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 44-Pin PLCC |
| CY7C372I-66JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 44-Pin PLCC |
| CY7C372I-66JI | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 44-Pin PLCC 制造商:QP Semiconductor 功能描述:CYP 7C372D DIE IT-PLCC 制造商:MAJOR 功能描述: |
| CY7C372I-66YMB | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells CMOS Technology 5V 44-Pin CLCC 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 1.6K Gates 64 Macro Cells 5V 44-Pin CLCC |
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