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參數(shù)資料
| 型號： | CY7C375I-83AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | UltraLogic 128-Macrocell Flash CPLD |
| 中文描述： | FLASH PLD, 19 ns, PQFP160 |
| 封裝： | PLASTIC, TQFP-160 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 431K |
| 代理商： | CY7C375I-83AC |
USE ULTRA37000
FOR ALL NEW DESIGNS
UltraLogic 128-Macrocell Flash CPLD
CY7C375i
Cypress Semiconductor Corporation
Document #: 38-03029 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised May 10, 2004
Features
128 macrocells in eight logic blocks
128 I/O pins
Five dedicated inputs including 4 clock pins
In-System Reprogrammable (ISR) Flash technology
— JTAG Interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
— f
MAX
= 125 MHz
— t
PD
= 10 ns
— t
S
= 5.5 ns
— t
CO
= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 160-pin TQFP, CQFP, and PGA packages
Functional Description
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C375i is
designed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
Like all of the UltraLogic F
LASH
370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally,
because of the superior routability of the F
LASH
370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
Logic Block Diagram
PIM
INPUT
MACROCELL
Clock
Inputs
Inputs
4
4
36
16
16
36
LOGIC
BLOCK
A
36
16
16
36
16 I/Os
36
36
36
16
16
36
16
16
64
64
4
1
INPUT/CLOCK
MACROCELLS
I/O
0
–I/O
15
LOGIC
BLOCK
C
LOGIC
BLOCK
B
LOGIC
BLOCK
D
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
F
LOGIC
BLOCK
E
I/O
16
–I/O
31
I/O
32
–I/O
47
I/O
48
–I/O
63
I/O
112
–I/O
127
I/O
96
–I/O
111
I/O
80
–I/O
95
I/O
64
–I/O
79
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
16 I/Os
Selection Guide
7C375i–125
10
5.5
6.5
125
7C375i–100
12
6
7
125
7C375i–83
15
8
8
125
7C375iL–83
15
8
8
75
7C375i–66
20
10
10
125
7C375iL–66
20
10
10
75
Unit
ns
ns
ns
mA
Maximum Propagation Delay
[1]
, t
PD
Minimum Set-Up, t
S
Maximum Clock to Output
[1]
, t
CO
Typical Supply Current, I
CC
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V
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