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參數資料
| 型號： | CY7C4241-25JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs |
| 中文描述： | 4K X 9 OTHER FIFO, 15 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數： | 1/18頁 |
| 文件大小： | 318K |
| 代理商： | CY7C4241-25JI |
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Cypress Semiconductor Corporation
Document #: 38-06016 Rev. *A
3901 North First Street
San Jose
CA 95134
408-943-2600
Revised March 6, 2202
Features
High-speed, low-power, First-In, First-Out (FIFO)
memories
—
64
×
9 (CY7C4421)
—
256
×
9 (CY7C4201)
—
512
×
9 (CY7C4211)
—
1K
×
9 (CY7C4221)
—
2K
×
9 (CY7C4231)
—
4K
×
9 (CY7C4241)
—
8K
×
9 (CY7C4251)
High-speed 100-MHz operation (10 ns Read/Write cycle
time)
Low power (I
CC
= 35 mA)
Fully asynchronous and simultaneous Read and Write
operation
Empty, Full, and Programmable Almost Empty and
Almost Full status flags
TTL-compatible
Expandable in width
Output Enable (OE) pin
Independent Read and Write enable pins
Center power and ground pins for reduced noise
Width-expansion capability
Space saving 7 mm
×
7 mm 32-pin TQFP
32-pin PLCC
Pin-compatible and functionally equivalent to
IDT72421, 72201, 72211, 72221, 72231, and 72241
Functional Description
The CY7C42X1 are high-speed, low-power FIFO memories
with clocked Read and Write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
Write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running Read clock (RCLK) and two
Read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The Read (RCLK) and Write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
Read/Write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Logic Block Diagram
Pin Configuration
THREE-STATE
OUTPUTREGISTER
Read
CONTROL
FLAG
LOGIC
Write
CONTROL
Write
POINTER
Read
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D0- 8
RCLK
EF
PAE
PAF
FF
Q0- 8
WEN1
WCLK
RS
OE
D64x 9
8kx 9
WEN2/LD
REN1 REN2
D
8
D
7
D
6
D
5
D
4
D
3
D
2
1
2
3
4
5
6
7
8
D
1
D
0
RCLK
REN2
GND
REN1
PAF
PAE
17
18
19
20
21
22
23
24
14 15 16
9 10 11 1213
31 30
32
2928 27
25
26
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
O
V
CC
Q
8
Q
7
Q
6
Q
5
WCLK
WEN2/LD
WEN1
R
TQFP
Top View
PLCC
Top View
D
1
D
0
RCLK
REN2
V
CC
Q
8
Q
7
Q
6
Q
5
D
8
D
7
D
6
D
5
D
4
D
3
GND
REN1
WCLK
WEN2/LD
D
2
PAF
PAE
5
6
7
8
9
10
11
12
13
OE
4 3 2 1
3130
32
21
22
23
24
27
26
28
29
25
14151617181920
WEN1
RS
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
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| CY7C421-25PI | 256/512/1K/2K/4K x 9 Asynchronous FIFO |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C4241V WAF | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4241V-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 4K x 9 32-Pin TQFP |
| CY7C4241V-15ACT | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 4K x 9 32-Pin TQFP T/R |
| CY7C4241V-15AXC | 功能描述:先進先出 4K X9 LO VLTG SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4241V-15AXCT | 功能描述:先進先出 4K X9 LO VLTG SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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