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參數資料
| 型號： | CY7C4261 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16Kx9 Deep Sync FIFOs(16Kx9 位深同步先進先出（FIFO）) |
| 中文描述： | 16Kx9同步FIFO的深度（16Kx9位深同步先進先出（FIFO）的） |
| 文件頁數： | 1/19頁 |
| 文件大小： | 320K |
| 代理商： | CY7C4261 |
16K/32Kx9 Deep Sync FIFOs
Functional Description
CY7C4261
CY7C4271
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
April 1995 - Revised November 4, 1997
Features
High-speed, low-power, first-in first-out (FIFO)
memories
16K x 9 (CY7C4261)
32K x 9 (CY7C4271)
0.5 micron CMOS for optimum speed/power
High-speed 100-MHz operation (10 ns read/write cycle
times)
Low power — I
CC
=35 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
TTL compatible
Output Enable (OE
)
pins
Independent read and write enable pins
Center power and ground pins for reduced noise
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Military temp SMD Offering- CY7C4271-15LMB
32-pin PLCC/LCC and 32-pin TQFP
Pin-compatible density upgrade to CY7C42X1 family
Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
The CY7C4261/71 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 9 bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and two write-en-
able pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into the
FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD
is held active, data is continually written into the FIFO on each WCLK
cycle. The output port is controlled in a similar manner by a free-run-
ning read clock (RCLK) and two read enable pins (REN1, REN2). In
addition, the CY7C4261/71 has an output enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for single-clock
operation or the two clocks may be run independently for asynchro-
nous read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable input
for system control, while the other enable is controlled by ex-
pansion logic to direct the flow of data.
LogicBlock Diagram
Pin Configuration
4261–1
4261–2
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0
8
RCLK
EF
PAE
PAF
FF
Q
0
8
WEN1
WCLK
RS
OE
RAM
16Kx 9
WEN2/LD
REN1 REN2
PLCC/LCC
Top View
4261–3
D
1
D
0
PAF
PAE
RCLK
REN2
V
CC
Q
8
Q
7
Q
6
Q
5
D
8
D
7
D
6
D
5
D
4
D
3
GND
REN1
WCLK
WEN2/LD
D
2
D
8
D
7
D
6
D
5
D
4
D
3
D
2
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
OE
4
3
2
1
31 30
32
D
1
D
0
PAF
PAE
RCLK
GND
REN1
REN2
21
22
23
24
27
26
28
29
25
14 15 16 17 18 19 20
17
18
19
20
21
22
23
24
14 15 16
9 10 11 12 13
31 30
32
29 28 27
25
26
WEN1
RS
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
F
Q
0
Q
1
Q
2
Q
3
Q
4
E
O
V
CC
Q
8
Q
7
Q
6
Q
5
WCLK
WEN2/LD
WEN1
R
TQFP
Top View
CY7C4261
CY7C4271
CY7C4261
CY7C4271
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C4265 | 8K/16Kx18 Deep Sync FIFOs |
| CY7C4255 | 8K/16Kx18 Deep Sync FIFOs |
| CY7C4271V | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| CY7C4271V-15JC | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
| CY7C4271V-25JC | 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C4261-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 9 32-Pin TQFP |
| CY7C4261-10JC | 制造商:Rochester Electronics LLC 功能描述:16K X 9 DEEP SYNC FIFO - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C4261-10JI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C4261-10JXI | 功能描述:先進先出 16Kx9 Deep SYNC 先進先出 IND RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4261-15JC | 功能描述:IC DEEP SYNC FIFO 16KX9 32-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:CY7C 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數據速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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