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參數資料
| 型號： | CY7C955 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | AX⑩ ATM-SONET/SDH Transceiver |
| 中文描述： | 斧⑩ATM-SONET/SDH收發器 |
| 文件頁數： | 1/78頁 |
| 文件大?。?/td> | 466K |
| 代理商： | CY7C955 |
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PRELIMINARY
AX ATM-SONET/SDH Transceiver
CY7C955
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 29, 1999
Features
WAN and LAN ATM physical layer device
Provides complete physical layer transport of ATM cells
at:
—STS
3c/ STM
1 rate of 155.52 MHz
—STS
1 rate of 51.84 MHz
Compliant with ATM Forum User Network Interface 3.1
specification
UTOPIA ATM interface
ATM cell processing including:
—HEC generation/verification
—Cell scrambling/descrambling
—Rate adaption/idle cell filtering
—Local Flow Control
—Cell alignment
SONET frame processing including:
—Compliant with Bellcore GR
253, I.432,
T1.105, and G.709 for Jitter Tolerance and Jitter
Generation
—Frame generation/recovery
—SONET scrambling/descrambling
—Frequency justification/pointer processing
Complete line interface including:
—Clock and data recovery
—Transmit timing derived from receiver or byte-rate
source
—SONET compliant PLL
—100K PECL compatible I/O
Alarm indications including:
—Loss Of Signal
—Out Of Frame, Loss Of Frame
—Line Far End Receive Failure
—Line Alarm Indication Signal
—B1 Parity Error
—Loss Of Cell Alignment
—Loss Of Receive Data
Controller interface for internal interrupt and
configuration registers including:
—Error monitoring
—Status indication
—Device configuration
0.65
μ
Low Power CMOS
128-pin PQFP
Functional Description
The Cypress Semiconductor CY7C955 is a Transceiver chip
designed to carry ATM cells across SONET/SDH systems.
On the transmit side, ATM cells coming from the Utopia inter-
face are being mapped into SONET/SDH frames and then se-
rialized for transmission over fiber or twisted pair (through an
optical module or an equalizer chip).
On the receive side, serial SONET/SDH datastreams coming
from an optical module or an equalizer chip are being recov-
ered by the intergrated clock and data recovery phase-locked
loop, framed, processed, and presented as parallel ATM cells
on the Receive Utopia Interface.
The CY7C955 can be used in a Network Interface Card (NIC)
design to connect the segmentation and Reassembly (SAR)
chip to the optical modules or equalizer chip.
The CY7C955 can also be used in work group or enterprise
switches to connect the I/O FIFOs of the switch fabric to the
optical module or equalizer in the interface boards.
The applications of the CY7C955 include adapters, switches,
routers, hubs, and proprietary systems.
TABLE OF CONTENTS
Features
Functional Description
Pin Descriptions
Pin Configuration
Description
Transmit Section
Receive Section
Controller Interface (CI)
Loopback Operation
SONET Overhead Description
CY7C955 Register Map
Electrical Characteristics
Capacitance
AC Test Loads and Waveforms
Switching Characteristics
1
1
2
7
8
8
10
12
16
17
18
60
61
61
61
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C955-NI | AX⑩ ATM-SONET/SDH Transceiver |
| CY7C960-NC | CAP 1800PF 100V 10% X7R AXIAL BULK S-MIL-PRF-39014 |
| CY7C960 | Low Cost VMEbus Interface Controller Family |
| CY7C960-ASC | Low Cost VMEbus Interface Controller Family |
| CY7C960-UM | Low Cost VMEbus Interface Controller Family |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C955-NC | 制造商:Cypress Semiconductor 功能描述:SONET Transceiver, AX ATM-SONET/SDH Transceiver |
| CY7C960-UMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C9611-NC | 功能描述:IC PHYSICAL LAYER DEVICE RoHS:否 類別:未定義的類別 >> 其它 系列:* 標準包裝:1 系列:* 其它名稱:MS305720A |
| CY7C964A-GMB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C964AUM | 制造商: 功能描述: 制造商:CY 功能描述: 制造商:undefined 功能描述: |
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