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參數資料
| 型號： | CYU01M16SCG-70BVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16-Mbit (1M x 16) Pseudo Static RAM |
| 中文描述： | 1M X 16 PSEUDO STATIC RAM, 70 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 502K |
| 代理商： | CYU01M16SCG-70BVXI |
PRELIMINARY
16-Mbit (1M x 16) Pseudo Static RAM
CYU01M16SCG
MoBL3
Cypress Semiconductor Corporation
Document #: 001-09739 Rev. **
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 7, 2006
Features
Wide voltage range: 2.2V–3.6V
Access Time: 70 ns
Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = f
max
Ultra low standby power
Automatic power-down when deselected
CMOS for optimum speed/power
Offered in a 48-ball BGA Package
Operating Temperature: –40°C to +85°C
Functional Description
[1]
The CYU01M16SCG is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE
1
HIGH or
CE
2
LOW or both BHE and BLE are HIGH). The input/output
pins (I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected (CE
1
HIGH or CE
2
LOW), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE
1
LOW and CE
2
HIGH and WE LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
19
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and
CE
2
HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
.
Refer to the truth table for a complete description of read and
write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
1M x 16
RAM Array
I/O
0
–I/O
7
COLUMN DECODER
S
DATA IN DRIVERS
OE
I/O
8
–I/O
15
WE
BLE
BHE
R
Power-Down
Circuit
BHE
BLE
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
7
A
6
A
5
A
4
A
3
A
19
CE
2
CE
1
CE
2
CE
1
A
2
A
1
A
0
Logic Block Diagram
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