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型號	廠商	描述
ep1k50fi256-1f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN
ep1k50fi256-1p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN
ep1k50fi256-1x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi256-2dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi256-2p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi256-2x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi256-3f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi484-1dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qc208-2f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qc208-2p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qc208-3f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qi208-1dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		250mA Single LDO with Low IQ, Low Noise and High PSRR LDO; Temperature Range: -40°C to 85°C; Package: 6-uTDFN T&R
ep1k50qi208-1f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qi208-1p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qi208-1x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qi208-2dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP); Temperature Range: -40°C to 85°C; Package: 5-SC-70 T&R
ep1k50qi208-2f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qi208-2p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qi208-2x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50qi208-3f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50tc144-1dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP); Temperature Range: -40°C to 85°C; Package: 5-SOT-23 T&R
ep1k50tc144-1f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50tc144-1p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP); Temperature Range: -40°C to 85°C; Package: 5-SC-70 T&R
ep1k50tc144-1x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50tc144-2dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50tc144-2f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP); Temperature Range: -40°C to 85°C; Package: 6-SC-70 T&R
ep1k50tc144-2p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP); Temperature Range: -40°C to 85°C; Package: 6-SC-70 T&R
ep1k50tc144-2x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP); Temperature Range: -40°C to 85°C; Package: 6-SOT-23 T&R
ep1k50tc144-3f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Single Volatile 32-Tap Digitally Controlled Potentiometer (XDCP); Temperature Range: -40°C to 85°C; Package: 6-SOT-23 T&R
ep1k50ti144-1dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc256-1dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Dual LDO with Low Noise, Low IQ, and High PSRR; Temperature Range: -40°C to 85°C; Package: 10-DFN
ep1k50fc256-1f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc256-1p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc256-1x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc256-2dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc256-2f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc256-2p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc256-2x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc256-3f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc484-1dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc484-1f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc484-1p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc484-1x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc484-2dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fc484-2f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi484-1f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi484-1p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi484-1x 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi484-2dx 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)
ep1k50fi484-2f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18		Field Programmable Gate Array (FPGA)

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