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參數(shù)資料
| 型號： | DC1370A-K |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/34頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 40MSPS LTC2257-12 |
| 軟件下載： | QuikEval II System |
| 設(shè)計資源： | DC1370A Design Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 相關(guān)產(chǎn)品： | DC718C-ND - DEMO QUIKEVAL-II DATA |
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LTC2258-12
LTC2257-12/LTC2256-12
25
225812fd
For more information www.linear.com/LTC2258-12
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11). The alternate
bit polarity mode is independent of the digital output
randomizer—either, both or neither function can be on
at the same time. When alternate bit polarity mode is on,
the data format is offset binary and the 2’s complement
control bit has no effect. The alternate bit polarity mode is
enabledbyseriallyprogrammingmodecontrolregisterA4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D11-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 1010101010101
to 0101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially program-
mingmodecontrolregisterA3.Alldigitaloutputsincluding
OFandCLKOUTaredisabled.Thehighimpedancedisabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down,resultingin0.5mWpowerconsumption.Sleepmode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
InnapmodetheA/Dcoreispowereddownwhiletheinternal
referencecircuitsstayactive,allowingfasterwake-upthan
from sleep mode. Recovering from nap mode requires at
least 100 clock cycles. If the application demands very
accurate DC settling then an additional 50s should be
allowedsotheon-chipreferencescansettlefromtheslight
temperature shift caused by the change in supply current
as the A/D leaves nap mode. Nap mode is enabled by mode
control register A1 in the serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2258-12/LTC2257-12/
LTC2256-12 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
Theparallelinterfaceismorelimitedandcanonlyprogram
some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
applicaTions inForMaTion
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