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參數資料
| 型號： | DC1620A-I |
| 廠商： | Linear Technology |
| 文件頁數： | 15/38頁 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 80MSPS LTC2143-14 |
| 軟件下載： | QuikEval II System |
| 設計資源： | DC1620A Design Files DC1620A Schematic |
| 標準包裝： | 1 |
| 系列： | * |
| 相關產品： | DC890B-ND - BOARD USB DATA COLLECTION |
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LTC2145-14/
LTC2144-14/LTC2143-14
22
21454314fa
APPLICATIONS INFORMATION
VREF
REFH
SENSE
C1
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
SENSE FOR
0.625V < VSENSE < 1.300V
1.25V
REFL
INTERNAL ADC
HIGH REFERENCE
BUFFER
21454314 F08a
LTC2145-14
5Ω
0.8x
DIFF AMP
INTERNAL ADC
LOW REFERENCE
C1: 2.2μF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
1.25V BANDGAP
REFERENCE
0.625V
RANGE
DETECT
AND
CONTROL
2.2μF
C2
0.1μF
C3
0.1μF
+
–
+
Figure 8a. Reference Circuit
SENSE
1.25V
EXTERNAL
REFERENCE
2.2μF
1μF
VREF
21454314 F09
LTC2145-14
Figure 9. Using an External 1.25V Reference
REFH
REFL
21454314 F08b
LTC2145-14
CAPACITORS ARE 0402 PACKAGE SIZE
C3
0.1μF
C1
2.2μF
C2
0.1μF
Figure 8b. Alternative REFH/REFL Bypass Circuit
Figure 8c. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8a
Alternatively, C1 can be replaced by a standard 2.2μF
capacitor between REFH and REFL (see Figure 8b). The
capacitors should be as close to the pins as possible (not
on the back side of the circuit board).
Figure 8c and Figure 8d show the recommended circuit
board layout for the REFH/REFL bypass capacitors. Note
that in Figure 8c, every pin of the interdigitated capacitor
(C1) is connected since the pins are not internally connected
Figure 8d. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8b
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals – do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for si-
nusoidal, PECL, or LVDS encode inputs (Figure 12 and
Figure 13). The encode inputs are internally biased to 1.2V
in some vendors’ capacitors. In Figure 8d the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
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