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參數資料
| 型號： | DEM-VSP2232Y |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CCD SIGNAL PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數碼相機 |
| 文件頁數： | 3/19頁 |
| 文件大小： | 248K |
| 代理商： | DEM-VSP2232Y |
VSP2232
SLAS320
–
MAY 2001
3
www.ti.com
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
ADCCK
B0(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11(MSB)
BYP
BYPM
BYPP2
CCDIN
CLPDM
CLPOB
CM
COB
DRVDD
DRVGND
GNDA
NO.
16
1
2
3
4
5
6
7
8
9
10
11
12
31
32
29
30
23
20
37
28
13
14
DI
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
AO
AO
AO
AI
DI
DI
AO
AO
P
P
P
Master clock, See Note 1
A/D converter output, Bit 0 (LSB)
A/D converter output, Bit 1
A/D converter output, Bit 2
A/D converter output, Bit 3
A/D converter output, Bit 4
A/D converter output, Bit 5
A/D converter output, Bit 6
A/D converter output, Bit 7
A/D converter output, Bit 8
A/D converter output, Bit 9
A/D converter output, Bit 10
A/D converter output, Bit 11 (MSB)
Internal reference C (bypass to ground), See Note 2
Internal reference N (bypass to ground), See Note 3
Internal reference P (bypass to ground), See Note 3
CCD signal input
Dummy pixel clamp pulse (Default = Active low), See Note 4
Optical black clamp pulse (Default = Active low), See Note 4
A/D converter common mode voltage (bypass to ground), See Note 2
Optical black clamp loop reference (bypass to ground), See Note 5
Power supply. Exclusively for digital output
Digital ground. Exclusively for digital output
Analog ground
15, 17, 25, 26, 35, 36,
41, 42
NC
PBLK
43, 44
19
Should be left open
Preblanking
High = Normal operation mode
Low = Preblanking mode: Digital output all zero
A/D converter negative reference (bypass to ground), See Note 2
A/D converter positive reference (bypass to ground), See Note 2
Asynchronous system reset (active low)
Clock for serial data shift (triggered at the rising edge)
Serial data input
CDS reference level sampling pulse (Default = Active low), See Note 4
CDS Data level sampling pulse (Default = Active low), See Note 4
DI
REFN
REFP
RESET
SCLK
SDATA
SHP
SHD
Designators in TYPE Column: P
–
power supply and ground, DI
–
digital input, DO
–
digital output, AI
–
analog input, AO
–
analog output
NOTES:
1. There are two options to drive the A/D converter:
a). External drive mode: The master clock (ADCCK) drives A/D converter directly.
b). Internal drive mode: The clock internally generated by on-chip timing control circuit using SHP and SHD signals drives A/D
converter.
2. BYP, CM, REFN, and REFP should be connected to ground using a bypass capacitor (0.1
μ
F). Refer to v
oltage reference
for details.
3. BYPM, BYPP2 should be connected to ground using a bypass capacitor with a recommend value of 200 pF to 600 pF. However,
this depends on the application environment. Refer to
voltage reference
for details.
4. Refer to
serial interface
for details.
5. COB should be connected to ground using a bypass capacitor with a recommend value of 0.1
μ
F to 0.22
μ
F. However, this depends
on the application environment. Refer to
optical black level clamp loop
for details.
39
38
45
48
47
21
22
AO
AO
DI
DI
DI
DI
DI
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