
MOTOROLA
Chapter 3. DINK32 Commands
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GPIC
gpic mask 4 23 - Mask the GPP[23] interrupt in the
GPPInterrupt Mask register
gpic unmask 0 24 - Unmask interrupts from GPP7_0 in the Main
Interrupt Mask High register
3.28.1 DINK32 GPIC Initialization Sequence
DINK32 [MPC7450 #0] >>gpic init
GPIC: Initialize GPIC
GPIC: In gpicInit()
GPIC: Disable External Interrupts
GPIC: Mask all external interrupt sources
GPIC: Clear all possible GPP interrupts
GPIC: Setup MPPs
GPIC: MPP[22] = GPP[22] = Super I_O Interrupt
GPIC: MPP[9:6] = GPP[9:6] = PCI 0 Slot 3-0 Interrupts
GPIC: MPP[13:10] = GPP[13:10] = PCI 1 Slot 3-0 Interrupts
GPIC: MPP[30] = GPP[30] = CPU1 Cross-Processor Interrupt Input
GPIC: MPP[4] = GPP[4] = CPU0 Cross-Processor Interrupt Input
GPIC: MPP[31] = GPP[31] = CPU1 Cross-Processor Interrupt Output
GPIC: MPP[5] = GPP[5] = CPU0 Cross-Processor Interrupt Output
GPIC: Setup GPPs
GPIC: GPP[22] = Super I_O = Input, Active High, Int enabled
GPIC: GPP[9:6] = PCI0 Slot 3-0 = Input, Active Low, Int enabled
GPIC: GPP[13:10] = PCI1 Slot 3-0 = Input, Active Low, Int enabled
GPIC: GPP[30] = CPU1 CPI = Input, Active High, Int enabled
GPIC: GPP[4] = CPU0 CPI = Input, Active High, Int enabled
GPIC: GPP[31] = CPU1 CPI = Output, Active High
GPIC: GPP[5] = CPU0 CPI = Output, Active High
GPIC: Setup Timer0 to interrupt CPU0 for sleep demo
GPIC: Setup Timer1 to interrupt CPU0
GPIC: User must enable/disable with ‘gpic tmcon 1 [1|0]’
GPIC: Timer Count = 0x0FFFFFFF
GPIC: Setup Timer2 to interrupt CPU1 for sleep demo
GPIC: Setup Timer3 to interrupt CPU1
GPIC: User must enable/disable with ‘gpic tmcon 3 [1|0]’
GPIC: Timer Count = 0x0FFFFFFF
GPIC: Unmask interrupts to CPUINT* (CPU0)
GPIC: Unmask GPP[23:16]
GPIC: Unmask GPP[15:8]
GPIC: Unmask GPP[7:0]
GPIC: Unmask Timer0
GPIC: Unmask interrupts to INT1* (CPU1)
GPIC: Unmask GPP[31:24]
F
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