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參數資料
| 型號： | DIR1701E2K |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數字音頻接口接收機 |
| 文件頁數： | 6/19頁 |
| 文件大小： | 290K |
| 代理商： | DIR1701E2K |
DIR1701
SLAS331
–
APRIL 2001
6
www.ti.com
basic operation theory
The DIR1701 has two PLLs, PLL1 and PLL2. The SpAct (Sampling Period Adaptive Controlled Tracking)
system is a newly developed clock recovery architecture, giving very low jitter clock from S/PDIF data input. The
DIR1701 requires a system clock input for operation of SpAct; internal PLL1 provides a 100 MHz execution
clock. The system clock can be obtained by either connecting a suitable crystal resonator at the XTI/XTO pins
or applying an external clock input at the XTI pin as shown in Figure 1. Internal PLL2 generates the system clock
SCKO by using the output signal of the SpAct frequency estimator.
When the S/PDIF input signal ceases, SCKO holds the latest tracked frequency. Also, the DIR1701 indicates
the unlocked state by a HIGH level output at the UNLOCK pin. When the S/PDIF signal restarts, the PLL will
lock in around 1ms with very low jitter, using the SpAct estimator. Then the DIR1701 indicates the locked status
by a LOW level output at the UNLOCK pin. In this status, the BRATE pins indicate the actual bit rate of the
incoming S/PDIF signal.
Crystal
C1
DIR1701
XTO
XTI
Open
DIR1701
XTO
XTI
C2
R1 = 1 M
,
C1, C2 = 10 TO 33 pF
Crystal Resonator Connection
XTAL
OSC
CIR
XTAL
OSC
CIR
External Clock
R1
External Clock Input
Figure 1. System Clock Connections
system clock output
The primary function of the DIR1701 is to recover audio data and a low jitter clock from a digital audio
transmission line. The clocks that can be generated are SCKO (128/256/384/512 f
S
, shown in Table 1), BCKO
(64 f
S
), and LRCKO (1 f
S
). SCKO is the output of the voltage controlled oscillator (VCO) in an analog PLL. The
PLL function consists of a VCO, phase and frequency detector, and a external second-order loop filter. The
closed-loop transfer function, which specifies the PLL jitter attenuation characteristics, is shown in Figure 2.
The crystal frequency should be defined for internal PLL by connecting the BRSEL pin to one of the output pins
BFRAME or CSBIT as shown in Table 2. A 12 MHz crystal resonator can be used for 128f
S
(CSBIT), 256f
S
(OPEN) and 384f
S
(BFRAME). And a 16 MHz crystal resonator is used for 512f
S
(BFRAME). The system clock
frequency can be set by control data at SCF0, SCF1 pin (shown in Table 3); this data must be stable before reset
is applied.
Table 4 shows the state of the system and the condition of audio clocks and flags. Required accuracy of system
clock by either crystal resonator or external clock input is
±
500 ppm.
Table 1. Generated System Clock (SCKO) Frequencies
SAMPLING
RATE
128 fS
256 fS
384 fS
512 fS
32 kHz
4.096 MHz
8.192 MHz
12.288 MHz
16.384 MHz
44.1 kHz
5.6448 MHz
11.2896 MHz
16.9344 MHz
22.5792 MHz
48 kHz
6.144 MHz
12.288 MHz
18.432 MHz
24.576 MHz
88.2kHz
11.2896 MHz
22.5792 MHz
33.8688 MHz
45.1584 MHz
96 kHz
12.288 MHz
24.576 MHz
36.864 MHz
49.152 MHz
相關PDF資料 |
PDF描述 |
|---|---|
| DIR1701 | DIGITAL AUDIO INTERFACE RECEIVER |
| DIR1701E | DIGITAL AUDIO INTERFACE RECEIVER |
| DIR1703 | DIGITAL AUDIO INTERFACE RECEIVER |
| DIR1703E | DIGITAL AUDIO INTERFACE RECEIVER |
| DISADVANTAGE | Disadvantage of On-Chip Transient Protection (105k) |
相關代理商/技術參數 |
參數描述 |
|---|---|
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| DIR1703E | 功能描述:IC DIGTAL AUD INTRFC RCVR 28SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發器 系列:- 標準包裝:1,240 系列:GD 類型:收發器 驅動器/接收器數:3/5 規程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:20-DIP（0.300"，7.62mm） 供應商設備封裝:20-PDIP 包裝:管件 |
| DIR1703E/2K | 制造商:Texas Instruments 功能描述:Audio Interface Receiver 28-Pin SSOP T/R 制造商:Texas Instruments 功能描述:AUD INTRFC RCVR 28SSOP - Tape and Reel |
| DIR-600/E | 制造商:D-Link Networks 功能描述: |
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