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參數(shù)資料
| 型號： | DJIXE972MLAA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 16/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXE972MLAA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
16
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
Table 4
lists signal descriptions of the LXT972M Transceiver MII data interface pins.
Table 4. Intel
LXT972M Transceiver MII Data Interface Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
47
46
45
44
TXD3
TXD2
TXD1
TXD0
I
Transmit Data.
TXD is a group of parallel data signals that are driven by the MAC.
TXD[3:0] transition synchronously with respect to TX_CLK.
TXD[0] is the least-significant bit.
43
TX_EN
I
Transmit Enable.
The MAC asserts this signal when it drives valid data on TXD.
This signal must be synchronized to TX_CLK.
42
TX_CLK
O
Transmit Clock.
TX_CLK is sourced by the PHY in both 10 and 100 Mbps
operations.
2.5 MHz for 10 Mbps operation
25 MHz for 100 Mbps operation.
33
34
35
36
RXD3
RXD2
RXD1
RXD0
O
Receive Data.
RXD is a group
of parallel signals that transition synchronously with
respect to RX_CLK.
RXD[0] is the least-significant bit.
37
RX_DV
O
Receive Data Valid.
The LXT972M Transceiver asserts this signal when it drives valid
data on RXD.
This output is synchronous to RX_CLK.
41
RX_ER
O
Receive Error.
Signals a receive error condition has occurred.
This output is synchronous to RX_CLK.
40
RX_CLK
O
Receive Clock.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
For details, see
“Clock Requirements” on page 28
in
Chapter 5.0,
“Functional Description”
.
48
COL
O
Collision Detected
.
The LXT972M Transceiver asserts this output when a collision is
detected.
This output remains High for the duration of the collision.
This signal is asynchronous and is inactive during full- duplex
operation.
1
CRS
O
Carrier Sense
.
During half-duplex operation (Register bit 0.8 = 0), the LXT972M
Transceiver asserts this output when either transmitting or receiving
data packets.
During full-duplex operation (Register bit 0.8 = 1), CRS is asserted
only during receive.
CRS assertion is asynchronous with respect to RX_CLK. CRS is
de-asserted on loss of carrier, synchronous to RX_CLK.
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| DJIXE972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MLEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MNAA4 | Single-Port 10/100 Mbps PHY Transceiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXE972MLCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MLEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MNAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MNCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXE972MNEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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