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參數(shù)資料
| 型號： | DJIXF972MNEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 4/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXF972MNEA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
4
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.8.6
5.8.7
5.8.8
Monitoring Operations.........................................................................................52
5.9.1
Monitoring Auto-Negotiation...................................................................52
5.9.2
Monitoring Next Page Exchange............................................................52
5.9.3
LED Functions........................................................................................53
5.9.4
LED Pulse Stretching.............................................................................54
Boundary Scan (JTAG 1149.1) Functions ..........................................................55
5.10.1 Boundary Scan Interface........................................................................55
5.10.2 State Machine ........................................................................................55
5.10.3 Instruction Register ................................................................................55
5.10.4 Boundary Scan Register ........................................................................56
5.10.5 Device ID Register .................................................................................56
10BASE-T SQE (Heartbeat) ..................................................................51
10BASE-T Jabber ..................................................................................51
10BASE-T Polarity Correction................................................................51
5.9
5.10
6.0
Application Information.....................................................................................................57
6.1
Magnetics Information.........................................................................................57
6.2
Typical Twisted-Pair Interface.............................................................................57
7.0
Electrical Specifications ...................................................................................................61
7.1
Electrical Parameters..........................................................................................61
7.2
Timing Diagrams.................................................................................................65
8.0
Register Definitions - IEEE Base Registers .....................................................................75
9.0
Register Definitions - Product-Specific Registers ............................................................83
10.0
Intel
LXT972M Transceiver Package Specifications......................................................90
10.1
Top Label Markings.............................................................................................91
11.0
Product Ordering Information...........................................................................................92
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Intel
LXT972M Transceiver Block Diagram.......................................................11
Pin Assignments for Intel
LXT972M Transceiver 48-Pin LQFP Package .........12
Management Interface Read Frame Structure ...................................................27
Management Interface Write Frame Structure ...................................................27
Initialization Sequence for Intel
LXT972M Transceiver.....................................30
Link Establishment Overview).............................................................................34
Clocking for 10BASE-T ......................................................................................37
Clocking for 100BASE-X ....................................................................................37
Clocking for Link Down Clock Transition ............................................................38
Intel
LXT972M Transceiver Loopback Paths ....................................................40
100BASE-X Frame Format ................................................................................41
100BASE-TX Data Path .....................................................................................42
100BASE-TX Reception with No Errors .............................................................43
100BASE-TX Reception with Invalid Symbol .....................................................43
100BASE-TX Transmission with No Errors ........................................................44
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXF972MPAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MPCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MPEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MQAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MQCA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXF972MPAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MPCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MPEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MQAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXF972MQCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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