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參數(shù)資料
| 型號： | DJIXP972MEEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 25/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXP972MEEA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
25
5.2.2
MII Data Interface
The LXT972M Transceiver supports a standard Media Independent Interface (MII). The MII
consists of a data interface and a management interface. The MII Data Interface passes data
between the LXT972M Transceiver and a Media Access Controller (MAC). Separate parallel buses
are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The
speed is set automatically, once the operating conditions of the network link have been determined.
For details, see
Section 5.6, “MII Operation” on page 36
.
Increased MII Drive Strength.
A higher Media Independent Interface (MII) drive strength may
be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive
loads, through multiple vias, or through a connector. The MII drive strength in the LXT972M
Transceiver can be increased by setting Register bit 26.11 through software control. Setting
Register bit 26.11 = 1 through the MDC/MDIO interface sets the MII pins (RXD[3:0], RX_DV,
RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive strength.
5.2.3
Configuration Management Interface
The LXT972M Transceiver provides both an MDIO interface and a reduced hardware control
interface for device configuration and management.
5.2.3.1
MDIO Management Interface
MDIO management interface topics include the following:
Section 5.2.3.1.1, “MDIO Addressing for Intel LXT972M Transceiver”
Section 5.2.3.1.2, “MDIO Frame Structure”
The LXT972M Transceiver supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT972M Transceiver. The MDIO interface consists of a
physical connection, a specific protocol that runs across the connection, and an internal set of
addressable registers.
Some registers are required and their functions are defined by the IEEE 802.3 standard. The
LXT972M Transceiver also supports additional registers for expanded functionality. The
LXT972M Transceiver supports multiple internal registers, each of which is 16 bits wide. Specific
register bits are referenced using an “X.Y” notation, where X is the register number (0-31) and Y is
the bit number (0-15).
5.2.3.1.1
MDIO Addressing for Intel
LXT972M Transceiver
The MDIO addressing protocol allows a controller to communicate with multiple LXT972M
Transceivers.As listed in
Table 12
, pins ADDR[1:0] determine the PHY device address that is
selected.
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| DJIXP972MHEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MKAA4 | Single-Port 10/100 Mbps PHY Transceiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DJIXP972MHAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MHCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MHEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MKAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MKCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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