- 您現在的位置：買賣IC網 > PDF目錄376726 > DJIXP972MEEA4 (Intel Corp.) Single-Port 10/100 Mbps PHY Transceiver PDF資料下載
參數資料
| 型號： | DJIXP972MEEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 50/92頁 |
| 文件大小： | 666K |
| 代理商： | DJIXP972MEEA4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
50
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.8
10 Mbps Operation
The LXT972M Transceiver operates as a standard 10BASE-T transceiver and supports standard
10 Mbps functions. During 10BASE-T operation, the LXT972M Transceiver transmits and
receives Manchester-encoded data across the network link. When the MAC is not actively
transmitting data, the LXT972M Transceiver drives link pulses onto the line.
In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded
signals received from the network are decoded by the LXT972M Transceiver and sent across the
MII to the MAC.
Note:
5.8.1
10BASE-T Preamble Handling
The LXT972M Transceiver offers two options for preamble handling, selected by Register bit 16.5.
In 10BASE-T mode when Register bit 16.5 = 0, the LXT972M Transceiver strips the entire
preamble off of received packets. CRS is asserted coincident with the start of the preamble.
RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first
two nibbles driven by the LXT972M Transceiver are the SFD “5D” hex followed by the body
of the packet.
In 10BASE-T mode when Register bit 16.5 = 1, the LXT972M Transceiver passes the
preamble through the MII and asserts RX_DV and CRS simultaneously. (In 10BASE-T
loopback, the LXT972M Transceiver loops back whatever the MAC transmits to it, including
the preamble.)
5.8.2
10BASE-T Carrier Sense
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and CRS de-assertion
is based on reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion
to be synchronized with RX_DV de-assertion. For details, see
Table 51, “Configuration Register -
Address 16, Hex 10” on page 84
.
5.8.3
10BASE-T Dribble Bits
The LXT972M Transceiver handles dribble bits in all modes. If one to four dribble bits are
received, the nibble is passed across the MII, padded with ones if necessary. If five to seven
dribble bits are received, the second nibble is not sent to the MII bus.
相關PDF資料 |
PDF描述 |
|---|---|
| DJIXP972MHAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MHCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MHEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MKAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MKCA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJIXP972MHAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MHCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MHEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MKAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJIXP972MKCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
發布緊急采購，3分鐘左右您將得到回復。