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參數(shù)資料
| 型號(hào)： | DJLXT972MKEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 19/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MKEA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
19
Table 9
lists signal descriptions of the LXT972M Transceiver power, ground, and no-connect pins.
Table 10
lists signal descriptions of LXT972M Transceiver Joint Test Action Group (JTAG) pins.
Note:
If a JTAG port is not used, these pins do not need to be terminated.
Table 9. Intel
LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
13
GNDA
–
Analog Ground.
5, 9, 24,
25, 30,
38
GND
–
Ground Input/Output.
Ground return for digital I/O circuits (VCCIO).
6, 29
VCCIO
–
MII Power.
Requires either a 3.3 V or a 2.5 V supply. Must be supplied
from the same source used to power the MAC on the other
side of the MII.
For the LXT972M Transceiver, VCCIO is 3.3 V.
16
VCCA
–
Analog Power.
Requires a 3.3 V power supply.
39
VCCD
–
Digital Power.
Requires a 3.3 V power supply.
7, 8
NC
–
No Connection
.
These pins are not used and must not be terminated.
Table 10. Intel
LXT972M Transceiver JTAG Test Signal Descriptions
LQFP
Pin#
Symbol
Type
Signal Description
19
TDI
I
Test Data Input
.
Test data sampled with respect to the rising edge of TCK.
20
TDO
O
Test Data Output
.
Test data driven with respect to the falling edge of TCK.
21
TMS
I
Test Mode Select
.
22
TCK
I
Test Clock
.
Clock input for boundary scan.
23
TRST_L
I
Test Reset
.
This active-low test reset input is sourced by ATE.
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| DJLXT972MLAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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| DJLXT972MLEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MNAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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