- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376726 > DJLXT972MLAA4 (Intel Corp.) Single-Port 10/100 Mbps PHY Transceiver PDF資料下載
參數(shù)資料
| 型號： | DJLXT972MLAA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 31/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MLAA4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
31
5.4.1
MDIO Control Mode and Hardware Control Mode
In the MDIO Control mode, the LXT972M Transceiver reads the Hardware Control Interface pins
to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control
reverts to the MDIO interface.
The following modes are available using MDIO Control.
Force network link operation to:
— 100BASE-TX, Full-Duplex
— 100BASE-TX, Half-Duplex
— 10BASE-T, Full-Duplex
— 10BASE-T, Half-Duplex
Allow auto-negotiation/parallel-detection
On power-up or hardware reset, the LXT972M Transceiver reads the Hardware Control Interface
pins and sets the MDIO registers accordingly.
The following modes are available using the Hardware Control:
Auto-negotiation-enabled advertising, either:
— 10/100 BASE-T Full/Half Duplex
— 10/100 BASE-T Half Duplex
LXT972M Transceiver device ID enable
Link Hold-off
When the network link is forced to a specific configuration, the LXT972M Transceiver
immediately begins operating the network interface as commanded. When auto-negotiation is
enabled, the LXT972MTransceiver begins the auto-negotiation/parallel-detection operation.
5.4.2
Reduced-Power Modes
This section discusses the LXT972M Transceiver reduced-power modes.
5.4.2.1
Software Power Down
Software power-down control is provided by Register bit 0.11 in the Control Register. (See
Table 41 on page 76.)
During soft power-down, the following conditions are true:
The network port is shut down.
The MDIO registers remain accessible.
5.4.3
Reset for Intel
LXT972M Transceiver
The LXT972M Transceiver provides both hardware and software resets, each of which manage
differently the configuration control of auto-negotiation, speed, and duplex-mode selection.
For a software reset, Register bit 0.15 = 1. For register bit definitions used for software reset, see
Table 41, “Control Register - Address 0, Hex 0” on page 76
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJLXT972MLCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MNAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MNCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MNEA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJLXT972MLC.A4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MLEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MNAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MNCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。