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參數資料
| 型號： | DJLXT972MPCA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 22/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MPCA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
22
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.1
Device Overview
The LXT972M Transceiver is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps
and 100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly drives
either a 100BASE-TX line or a 10BASE-T line.
5.1.1
Comprehensive Functionality
The LXT972M Transceiver provides a standard Media Independent Interface (MII) for 10/100
MACs. The LXT972M Transceiver performs all functions of the Physical Coding Sublayer (PCS)
and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X
standard. It also performs all functions of the Physical Media Dependent (PMD) sublayer for
100BASE-TX connections.
If the LXT972M Transceiver is not set for forced operation, it uses auto-negotiation/parallel
detection to automatically determine line operating conditions. If the PHY device on the other side
of the link supports auto-negotiation, the LXT972M Transceiver auto-negotiates with it using Fast
Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT972M
Transceiver automatically detects the presence of either link pulses (10 Mbps PHY) or Idle
symbols (100 Mbps PHY) and sets its operating conditions accordingly.
The LXT972M Transceiver provides half-duplex and full-duplex operation at 100 Mbps and 10
Mbps.
5.1.2
Optimal Signal Processing Architecture
The LXT972M Transceiver incorporates high-efficiency Optimal Signal Processing (OSP) design
techniques, which combine optimal properties of digital and analog signal processing.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results
in improved receiver noise and cross-talk performance.
The OSP signal processing scheme also requires substantially less computational logic than
traditional DSP-based designs. This lowers power consumption and also reduces the logic
switching noise generated by DSP engines. This logic switching noise can be a considerable source
of EMI generated on the device’s power supplies.
The OSP-based LXT972M Transceiver provides improved data recovery, EMI performance, and
low power consumption.
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PDF描述 |
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| DJLXT972MPEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQAA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQCA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQEA4 | Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MTAA4 | Single-Port 10/100 Mbps PHY Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DJLXT972MPEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQCA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MQEA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
| DJLXT972MTAA4 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
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