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參數(shù)資料
| 型號： | DJLXT972MQEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 23/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MQEA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
23
5.2
Network Media / Protocol Support
This section includes the following:
Section 5.2.1, “10/100 Network Interface”
Section 5.2.2, “MII Data Interface”
Section 5.2.3, “Configuration Management Interface”
The LXT972M Transceiver supports both 10BASE-T and 100BASE-TX Ethernet over twisted-
pair.
5.2.1
10/100 Network Interface
The network interface port consists of two differential signal pairs. For specific pin assignments,
see
Chapter 4.0, “Signal Descriptions for Intel LXT972M Transceiver”
.
The LXT972M Transceiver output drivers can generate one of the following outputs:
100BASE-TX
10BASE-T
When not transmitting data, the LXT972M Transceiver generates IEEE 802.3-compliant link
pulses or idle code. Depending on the mode selected, input signals are decoded as one of the
following:
When not transmitting data, the LXT972M Transceiver generates IEEE 802.3-compliant link
pulses or idle code. Depending on the mode selected, input signals are decoded as one of the
following:
100BASE-TX
10BASE-T
Auto-negotiation/parallel detection or manual control is used to determine the speed of this
interface.
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相關(guān)代理商/技術(shù)參數(shù) |
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