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參數資料
| 型號： | DJLXT972MQEA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 36/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MQEA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
36
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5.6
MII Operation
This section includes the following topics:
Section 5.6.1, “MII Clocks”
Section 5.6.2, “Transmit Enable”
Section 5.6.3, “Receive Data Valid”
Section 5.6.4, “Carrier Sense”
Section 5.6.5, “Error Signals”
Section 5.6.6, “Collision”
Section 5.6.7, “Loopback”
The LXT972M Transceiver implements the Media Independent Interface (MII) as defined by the
IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the
LXT972M Transceiver (TXD), and for passing data received from the line (RXD) to the MAC.
Each channel has its own clock, data bus, and control signals.
The following signals are used to pass received data to the MAC:
COL
CRS
RX_CLK
RX_DV
RX_ER
RXD[3:0]
The following signals are used to transmit data from the MAC:
TX_CLK
TX_EN
TXD[3:0]
The LXT972M Transceiver supplies both clock signals as well as separate outputs for carrier sense
and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
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