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參數資料
| 型號： | DJLXT972MTAA4 |
| 廠商： | Intel Corp. |
| 英文描述： | Single-Port 10/100 Mbps PHY Transceiver |
| 中文描述： | 單端口10/100 Mbps的物理層收發器 |
| 文件頁數： | 85/92頁 |
| 文件大小： | 666K |
| 代理商： | DJLXT972MTAA4 |
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Intel
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
85
Table 52
lists register #2 status bits.
Table 52. Status Register #2 - Address 17, Hex 11
Bit
Name
Description
Type
1
Default
17.15
Reserved
Always 0.
RO
0
17.14
10/100 Mode
0 = LXT972M Transceiver is not operating
100BASE-TX mode.
1 = LXT972M Transceiver is operating in
100BASE-TX mode.
RO
0
17.13
Transmit Status
0 = LXT972M Transceiver is not transmitting a
packet.
1 = LXT972M Transceiver is transmitting a
packet.
RO
0
17.12
Receive Status
0 = LXT972M Transceiver is not receiving a
packet.
1 = LXT972M Transceiver is receiving a packet.
RO
0
17.11
Collision Status
0 = No collision.
1 = Collision is occurring.
RO
0
17.10
Link
0 = Link is down.
1 = Link is up.
RO
0
17.9
Duplex Mode
0 = Half-duplex.
1 = Full-duplex.
RO
0
17.8
Auto-Negotiation
0 = LXT972M Transceiver is in manual mode.
1 = LXT972M Transceiver is in auto-negotiation
mode.
RO
0
17.7
Auto-Negotiation
Complete
0 = Auto-negotiation process not completed.
1 = Auto-negotiation process completed.
This bit is valid only when auto negotiate is
enabled. The value is equivalent to the value of
Register bit 1.5.
RO
0
17.6
Reserved
Always 0.
RO
0
17.5
Polarity
0 = Polarity is not reversed.
1 = Polarity is reversed.
NOTE:
Polarity is not a valid status in 100 Mbps
mode.
RO
0
17.4
Pause
0 = The LXT972M Transceiver is not Pause
capable.
1 = The LXT972M Transceiver is Pause capable.
R
0
17:3
Error
0 = No error occurred
1 = Error occurred (Remote Fault, jabber, parallel
detect fault)
NOTE:
The register bit is cleared when the
registers that generate the error condition
are read.
RO
0
17:2
Reserved
Always 0.
RO
0
17:1
Reserved
Always 0.
RO
0
17.0
Reserved
Always 0.
RO
0
1. RO = Read Only. R/W = Read/Write
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