- 您現在的位置：買賣IC網 > PDF目錄16755 > DLP-FPGA-M (DLP Design Inc)MODULE USB-TO-FPGA TOOL W/MANUAL PDF資料下載
參數資料
| 型號： | DLP-FPGA-M |
| 廠商： | DLP Design Inc |
| 文件頁數： | 6/10頁 |
| 文件大小： | 0K |
| 描述： | MODULE USB-TO-FPGA TOOL W/MANUAL |
| 標準包裝： | 1 |
| 主要目的： | 接口，USB 至 FPGA |
| 嵌入式： | 是，FPGA / CPLD |
| 已用 IC / 零件： | FT2232D，XC3S250E-4TQ144 |
| 主要屬性： | USB 至 FPGA，40 I/O 引腳，SRAM: 128k x 8 |
| 次要屬性： | 手冊中有 4 個實驗室，250k 系統柵極，5.5k 邏輯單元 |
| 已供物品： | 板，手冊 |
| 相關產品： | XC3S250E-4TQG144I-ND - IC FPGA SPARTAN-3E 250K 144-TQFP 768-1010-6-ND - IC USB FS DUAL UART/FIFO 48-LQFP 768-1010-1-ND - IC USB FS DUAL UART/FIFO 48-LQFP 768-1010-2-ND - IC USB FS DUAL UART/FIFO 48-LQFP 122-1524-ND - IC SPARTAN-3E FPGA 250K 144TQFP |
| 其它名稱： | 813-1009 |
Rev. 1.4 (November 2010)
5
DLP Design, Inc.
8.0 USB DRIVERS
USB drivers for the following operating systems are available for download from the DLP Design
website at http://www.dlpdesign.com:
W
Wiin
nd
do
ow
ws
s X
XP
P x
x6
64
4
M
Ma
ac
c O
OS
SX
X
W
Wiin
nd
do
ow
ws
s S
Se
errv
ve
err 2
20
00
03
3
M
Ma
ac
c O
OS
S9
9
W
Wiin
nd
do
ow
ws
s 2
20
00
0
M
Ma
ac
c O
OS
S8
8
W
Wiin
nd
do
ow
ws
s 9
98
8,, M
ME
E
L
Liin
nu
ux
x
Notes:
1. The bit file load utility only runs on the Windows platforms.
2. The bit file load utility requires the use of USB channel A, and channel A is dedicated to this
function.
3. If you are using the dual-mode drivers from FTDI (CDM2.02.04) and wish to use the Virtual
COM Port (VCP) drivers for Channel B communications, then it may be necessary to disable
the D2XX drivers first via Device Manager. To do so, right click on the Channel B entry under
USB Controllers that appears when the DLP-FPGA is connected, select Properties, select the
Advanced tab, check the option for “Load VCP” and click OK. Once you unplug and then
replug the DLP-FPGA, a COM port should appear in Device Manager under Ports (COM &
LPT).
9.0 USING THE DLP-FPGA
Select a power source via Header Pins 23 and 24, and connect the DLP-FPGA to the PC to initiate
the loading of USB drivers. The easiest way to do this is to connect Pins 23 and 24 to each other.
This will result in operational power being taken from the host PC. Once the drivers are loaded, the
DLP-FPGA is ready for use.
FPGA
US
B
Pin 25
Pin 26
Top View (Interface Headers on bottom of PCB)
Pin 1
Pin 50
SRAM
相關PDF資料 |
PDF描述 |
|---|---|
| V300B36E150B | CONVERTER MOD DC/DC 36V 150W |
| V48C8E150BG2 | CONVERTER MOD DC/DC 8V 150W |
| SOIC14EV | BOARD EVAL 14SOIC/TSSOP/DIP |
| V48C8E150BG | CONVERTER MOD DC/DC 8V 150W |
| MCP73213EV-2SOVP | BOARD EVAL BATT CHARGER MCP73213 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DLPG12000 | 制造商:Dialight 功能描述: |
| DLP-H08-ASYNM-CX | 功能描述:開發軟件 ASYNC SERIAL COMM RoHS:否 制造商:Atollic Inc. 產品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| DLP-H12-EBYTE-CX | 功能描述:開發軟件 EXT BYTE I/O W RoHS:否 制造商:Atollic Inc. 產品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| DLP-H12-PWMMC-CX | 制造商:Freescale Semiconductor 功能描述:PWM FOR MOTOR Ctrl |
| DLP-HC8-PWMMC-CX | 制造商:Freescale Semiconductor 功能描述:PWM MOTOR CONTROL |
發布緊急采購，3分鐘左右您將得到回復。