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參數資料
| 型號： | DM74LS163AN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Binary Counters |
| 中文描述： | LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 103K |
| 代理商： | DM74LS163AN |
2000 Fairchild Semiconductor Corporation
DS006397
www.fairchildsemi.com
August 1986
Revised April 2000
D
DM74LS161A DM74LS163A
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. The DM74LS161A and DM74LS163A are 4-bit
binary counters. The carry output is decoded by means of
a NOR gate, thus preventing spikes during the normal
counting mode of operation. Synchronous operation is pro-
vided by having all flip-flops clocked simultaneously so that
the outputs change coincident with each other when so
instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting
spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the
four flip-flops on the rising (positive-going) edge of the
clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the DM74LS161A is asynchro-
nous; and a low level at the clear input sets all four of the
flip-flop outputs LOW, regardless of the levels of clock,
load, or enable inputs. The clear function for the
DM74LS163A is synchronous; and a low level at the clear
inputs sets all four of the flip-flop outputs LOW after the
next clock pulse, regardless of the levels of the enable
inputs. This synchronous clear allows the count length to
be modified easily, as decoding the maximum count
desired can be accomplished with one external NAND
gate. The gate output is connected to the clear input to
synchronously clear the counter to all low outputs.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output.
Both count-enable inputs (P and T) must be HIGH to count,
and input T is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high-
level output pulse with a duration approximately equal to
the high-level portion of the Q
A
output. This high-level over-
flow ripple carry pulse can be used to enable successive
cascaded stages. HIGH-to-LOW level transitions at the
enable P or T inputs may occur, regardless of the logic
level of the clock.
These counters feature a fully independent clock circuit.
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs. The function of the counter (whether enabled, dis-
abled, loading, or counting) will be dictated solely by the
conditions meeting the stable set-up and hold times.
Features
I
Synchronously programmable
I
Internal look-ahead for fast counting
I
Carry output for n-bit cascading
I
Synchronous counting
I
Load control line
I
Diode-clamped inputs
I
Typical propagation time, clock to Q output 14 ns
I
Typical clock frequency 32 MHz
I
Typical power dissipation 93 mW
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
DM74LS161AM
DM74LS161AN
DM74LS163AM
DM74LS163AN
Package Number
M16A
N16E
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
相關PDF資料 |
PDF描述 |
|---|---|
| DM74LS163AMX | Synchronous Up Counter |
| DM74LS164M | Quad Buffer with 3-STATE Outputs |
| DM74LS164 | 8-Bit Serial In/Parallel Out Shift Register(8位串行輸入/并行輸出的移位寄存器) |
| DM74LS164N | Quad Buffer with 3-STATE Outputs |
| DM74LS166M | Quad Buffer with 3-STATE Outputs; Package: TSSOP; No of Pins: 14; Container: Rail |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM74LS163AN/A+ | 制造商:Texas Instruments 功能描述: |
| DM74LS164 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74LS164M | 功能描述:計數器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS164MX | 功能描述:計數器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| DM74LS164N | 功能描述:計數器移位寄存器 8-Bit Serial Sht Reg RoHS:否 制造商:Texas Instruments 計數器類型: 計數順序:Serial to Serial/Parallel 電路數量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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