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參數資料
| 型號： | DM74S161N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Binary Counters |
| 中文描述： | S SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | 0.300 INCH, MS-001, PLASTIC, DIP-16 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 80K |
| 代理商： | DM74S161N |
2000 Fairchild Semiconductor Corporation
DS006471
www.fairchildsemi.com
August 1986
Revised April 2000
D
DM74S161
DM74S163
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. They are 4-bit binary counters. The carry output is
decoded by means of a NOR gate, thus preventing spikes
during the normal counting mode of operation. Synchro-
nous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with
each other when so instructed by the count enable inputs
and internal gating. This mode of operation eliminates the
output counting spikes which are normally associated with
asynchronous (ripple clock) counters. A buffered clock
input triggers the four flip-flops on the rising (positive-
going) edge of the clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a LOW level at the load input disables the
counter and causes the outputs to agree with the setup
data after the next clock pulse regardless of the levels of
the enable input.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output. Both
count-enable inputs (P and T) must be HIGH to count, and
input T is fed forward to enable the ripple carry output. The
ripple carry output thus enabled will produce a HIGH-level
output pulse with a duration approximately equal to the
HIGH-level portion of the Q
A
output. This HIGH-level over-
flow ripple carry pulse can be used to enable successive
cascaded stages.
Features
I
Synchronously programmable
I
Internal look-ahead for fast counting
I
Carry output for n-bit cascading
I
Synchronous counting
I
Load control line
I
Diode-clamped inputs
Ordering Code:
Connection Diagram
Order Number
DM74S161N
DM74S163N
Package Number
N16E
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
相關PDF資料 |
PDF描述 |
|---|---|
| DM74S163N | Synchronous 4-Bit Binary Counters |
| DM74S175N | Hex/Quad D Flip-Flop with Clear |
| DM74S174 | Hex/Quad D Flip-Flop with Clear |
| DM74S174N | Hex/Quad D Flip-Flop with Clear |
| DM74S182 | Look-Ahead Carry Generator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DM74S161N 83 | 制造商:National Semiconductor 功能描述:74S161 |
| DM74S161N 90 | 制造商:National Semiconductor 功能描述:74S161 |
| DM74S161N 91 | 制造商:National Semiconductor 功能描述:74S161 |
| DM74S161N83 | 制造商:National Semiconductor 功能描述:74S161 |
| DM74S161N90 | 制造商:National Semiconductor 功能描述:74S161 |
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