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參數資料
型號: DM74S175N
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Hex/Quad D Flip-Flop with Clear
中文描述: S SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
封裝: 0.300 INCH, PLASTIC, MS-001, DIP-16
文件頁數: 1/5頁
文件大小: 56K
代理商: DM74S175N
2000 Fairchild Semiconductor Corporation
DS006472
www.fairchildsemi.com
August 1986
Revised April 2000
D
DM74S174
DM74S175
Hex/Quad D Flip-Flop with Clear
General Description
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (DM74S175) versions feature comple-
mentary outputs from each flip-flop.
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a partic-
ular voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the HIGH or LOW level, the D input signal has no
effect at the output.
Features
I
DM74S174 contain six flip-flops with single-rail outputs.
I
DM74S175 contain four flip-flops with double-rail out-
puts.
I
Buffered clock and direct clear inputs
I
Individual data input to each flip-flop
I
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
I
Typical clock frequency 110 MHz
I
Typical power dissipation per flip-flop 75mW
Ordering Code:
Connection Diagrams
DM74S174
DM74S175
Order Number
DM74S174N
DM74S175N
Package Number
N16E
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
相關PDF資料
PDF描述
DM74S174 Hex/Quad D Flip-Flop with Clear
DM74S174N Hex/Quad D Flip-Flop with Clear
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