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參數(shù)資料
| 型號： | DM74S74 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs(帶預(yù)置、清零、互補輸出的雙正邊緣觸發(fā)D觸發(fā)器) |
| 中文描述： | 雙上升沿觸發(fā)D觸發(fā)器的預(yù)置，清除，互補輸出（帶預(yù)置，清零，互補輸出的雙正邊緣觸發(fā)?觸發(fā)器） |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 50K |
| 代理商： | DM74S74 |
2000 Fairchild Semiconductor Corporation
DS006457
www.fairchildsemi.com
August 1986
Revised April 2000
D
DM74S74
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The infor-
mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as setup and
hold times are not violated. A low logic level on the preset
or clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
L
=
LOW Logic Level
↑
=
Positive-going Transition
*
=
This configuration is nonstable; that is, it will not persist when either the
preset and/or clear inputs return to its inactive (HIGH) level.
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
Order Number
DM74S74M
DM74S74N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
L
D
X
X
X
H
L
X
Q
H
L
H*
H
L
Q
0
Q
L
H
H*
L
H
Q
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM74S74M | Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs |
| DM74S74N | Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs |
| DM74S74MX | Dual D-Type Flip-Flop |
| DM74S86 | Quad 2-Input Exclusive-OR Gate |
| DM74S86N | Quad 2-Input Exclusive-OR Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM74S74 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74S74M | 功能描述:觸發(fā)器 Dl D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74S74MX | 功能描述:觸發(fā)器 Dl D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74S74N | 功能描述:觸發(fā)器 Dl D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM74S86 DIE | 制造商:Texas Instruments 功能描述: |
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