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參數(shù)資料
| 型號： | DNC5X3125 |
| 廠商： | Lineage Power |
| 英文描述： | Gigabit Ethernet Transceiver Macrocell(千兆位以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器宏單元（千兆位以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 260K |
| 代理商： | DNC5X3125 |
Advance Data Sheet
March 2000
DNC5X3125
Gigabit Ethernet Transceiver Macrocell
Overview
The DNC5X3125 is a low-cost, low-power transceiver
macrocell. It is used for data transmission over fiber
or coaxial media in conformance with IEEE* 802.3z
Gigabit Ethernet specification and Fibre Channel
ANSI
X3T11 at 1.0 Gbits/s and 1.25 Gbits/s.
The transmitter section accepts parallel 10-bit
8b/10b encoded data that is latched on the rising
edge of TBC. It also accepts the low-speed, TTL
compatible system clock, REFCLK, and uses this
clock to synthesize the internal high-speed serial bit
clock. The serialized data is then available at the dif-
ferential PECL outputs, terminated in 50
or 75
to
drive either an optical transmitter or coaxial media.
The receive section receives high-speed serial data
at its differential PECL input port. This data is fed to
the digital clock recovery section, which generates a
recovered clock and retimes the data. The retimed
data is deserialized and presented as 10-bit parallel
data on the output port. A divided-down version of
the recovered clock, synchronous with parallel data
bytes, is also available as a TTL compatible output.
The receive section recognizes the comma character
and aligns the comma-containing byte on the word
boundary, when ENCDET = 1.
Features
I
Designed to operate in Ethernet, fibre channel,
FireWire
or backplane applications.
I
Operationally compliant to IEEE802.3z Gigabit
Ethernet specification.
I
Operationally compliant to Fibre Channel ANSI
X3T11. Provides FC-0 services at 1.0 Gbits/s—
1.25 Gbits/s (10-bit encoded data rate).
I
100 MHz—125 MHz differential or single-ended
reference clock.
I
10-bit parallel interface.
I
8b/10b encoded data.
I
High-speed comma character recognition (K28.1,
K28.5, K28.7) for latency-sensitive applications
and alignment to word boundary.
I
Two 50.0 MHz—62.5 MHz receive-byte clocks.
I
Single analog PLL design requires no external
components for the frequency synthesizer.
I
Novel digital data lock in receiver avoids the need
for multiple analog PLLs.
I
Expandable beyond single-channel SERDES.
I
PECL high-speed interface I/O for use with optical
transceiver or coaxial copper media.
I
Requires one external resistor for PECL output ref-
erence level definition.
I
Low-power digital 0.25 μm CMOS technology.
I
3.3 V ± 5% power supply.
I
0 °C—70 °C ambient temperature.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
ANSIis a registered trademark of American National Standards
Institute.
FireWireis a registered trademark of Apple Computer, Inc.
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