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參數(shù)資料
| 型號(hào)： | DS2172T |
| 英文描述： | Bit Error Rate Tester BERT |
| 中文描述： | 誤碼率測(cè)試儀誤碼 |
| 文件頁(yè)數(shù)： | 1/21頁(yè) |
| 文件大?。?/td> | 213K |
| 代理商： | DS2172T |
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051700
FEATURES
Generates/Detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systems
Operates at speeds from DC to 52 MHz
Programmable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 2
6
-1, 2
9
-1, 2
11
-1, 2
15
-1, 2
20
-1, 2
23
-1,
and 2
32
-1
Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in length
Large 32-bit error count and bit count
registers
Software programmable bit error insertion
Fully independent transmit and receive
sections
8-bit parallel control port
Detects test patterns with bit error rates up to
10
-2
PIN ASSIGNMENT
ORDERING INFORMATION
DS2172T
DS2172TN
(0
0
C to 70
0
C)
(-40
0
C to + 85
0
C)
DESCRIPTION
The DS2172 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)
conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS2172 operates at clock rates
ranging from DC to 52 MHz. This wide range of operating frequency allows the DS2172 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.
The DS2172 user-programmable pattern registers provide the unique ability to generate loopback patterns
required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS2172 can initiate the
loopback, run the test, check for errors, and finally deactivate the loopback.
The DS2172 consists of four functional blocks: the pattern generator, pattern detector, error counter, and
control interface. The DS2172 can be programmed to generate any pseudorandom pattern with length up
to 2
32
-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic
inputs can be used to configure the DS2172 for applications requiring gap clocking such as Fractional-T1,
Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the
DS2172 can insert single or 10
-1
to 10
-7
bit errors to verify equipment operation and connectivity.
DS2172
Bit Error Rate Tester (BERT)
www.dalsemi.com
TL
AD0
AD1
TEST
VSS
AD2
AD3
AD4
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
RL
RLOS
LC
VSS
VDD
INT
WR(R/W)
ALE(AS)
A
A
A
V
V
B
R
C
T
T
T
V
V
R
R
R
DS2172
32-Pin TQFP
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2172TN | Bit Error Rate Tester BERT |
| DS2172 | Bit Error Rate Tester BERT |
| DS2174DK | Enhanced Bit Error-Rate Tester Design Kit |
| DS2175S | PCM， Other/Special/Miscellaneous |
| DS2175SN | PCM， Other/Special/Miscellaneous |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2172T/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:IC TESTER BIT ERROR RATE 32-TQFP 制造商:Maxim Integrated Products 功能描述:Telecom ICs Bit Error Rate Tester (BERT) |
| DS2172T/T&R+ | 制造商:Maxim Integrated Products 功能描述:BERT 32P TQFP T&R LEAD FREE - Tape and Reel |
| DS2172T/T&R | 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2172T+ | 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2172T+T&R | 制造商:Maxim Integrated Products 功能描述:BIT ERROR RATE TESTER 32TQFP - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TESTER BIT ERROR RATE 32-TQFP 制造商:Maxim Integrated Products 功能描述:Telecom ICs Bit Error Rate Tester (BERT) |
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