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參數(shù)資料
| 型號： | EBD26UC6AKSA-7A-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | Single Pole Normally Open: 1-Form-A, 400V |
| 中文描述： | 32M X 64 DDR DRAM MODULE, 0.75 ns, ZMA200 |
| 封裝： | LEAD FREE, SODIMM-200 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大小： | 213K |
| 代理商： | EBD26UC6AKSA-7A-E |
Document No. E0605E10 (Ver. 1.0)
Date Published November 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2004
PRELIMINARY DATA SHEET
256MB DDR SDRAM SO-DIMM
EBD26UC6AKSA-E
(32M words
×
64 bits, 2 Ranks)
Description
The EBD26UC6AKSA is 32M words
×
64 bits, 2 ranks
Double Data Rate (DDR) SDRAM Small Outline Dual
In-line Memory Module, mounting 8 pieces of 256M
bits DDR SDRAM sealed in TSOP package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. This module
provides high density mounting without utilizing surface
mount technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 31.75mm
Lead pitch: 0.6mm
Lead-free
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs, outputs and DM are synchronized with
DQS
4 internal banks for concurrent operation
(Components)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8
μ
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBD26UC6AKSA-6B | 256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks) |
| EBD26UC6AKSA | Single Pole Normally Open: 1-Form-A |
| EBD26UC6AKSA-7A | Single Pole Normally Open: 1-Form-A, 800V |
| EBD26UC6AKSA-7B | Single Pole Normally Open: 1-Form-A |
| EBD26UC6AKSA-7B-E | Single Pole Normally Open: 1-Form-A, 600V |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBD26UC6AKSA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks) |
| EBD26UC6AKSA-7B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks) |
| EBD26UC6AKSA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks) |
| EBD26UC6AMSA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO-DIMM |
| EBD26UC6AMSA-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB DDR SDRAM SO-DIMM |
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