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參數資料
| 型號： | EBD52UC8AKFA-5-E |
| 廠商： | Elpida Memory, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:55; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:16-35 RoHS Compliant: No |
| 中文描述： | 512MB的DDR SDRAM的內存緩沖（6400字× 64位，2個等級） |
| 文件頁數： | 1/19頁 |
| 文件大小： | 190K |
| 代理商： | EBD52UC8AKFA-5-E |
Document No. E0601E10 (Ver. 1.0)
Date Published October 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004
PRELIMINARY DATA SHEET
512MB Unbuffered DDR SDRAM DIMM
EBD52UC8AKFA-5-E
(64M words
×
64 bits, 2 Ranks)
Description
The EBD52UC8AKFA is 64M words
×
64 bits, 2 ranks
Double Data Rate (DDR) SDRAM unbuffered module,
mounting 16 pieces of 256M bits DDR SDRAM sealed
in TSOP package. Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
Lead
-
free
2.5V power supply
Data rate: 400Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Components)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 3
Programmable output driver strength: normal/weak
Refresh cycles: (8192 refresh cycles /64ms)
7.8
μ
s maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
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| EBE10RD4AEFA-5C-E | 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank) |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EBD52UC8AMFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM |
| EBD52UC8AMFA-5 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM |
| EBD52UC8AMFA-5B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM |
| EBD52UC8AMFA-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered DDR SDRAM DIMM |
| EBD52UD6ADSA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks) |
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