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參數(shù)資料
| 型號： | EBE10RD4ABFA |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank) |
| 中文描述： | 1GB的注冊DDR2 SDRAM DIMM內(nèi)存（128M的字× 72位，1個等級） |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 190K |
| 代理商： | EBE10RD4ABFA |
Document No. E0644E30 (Ver. 3.0)
Date Published April 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
DATA SHEET
1GB Registered DDR2 SDRAM DIMM
EBE10RD4AEFA
(128M words
×
72 bits, 1 Rank)
Description
The EBE10RD4AEFA is a 128M words
×
72 bits, 1
rank DDR2 SDRAM Module, mounting 18 pieces of
DDR2 SDRAM sealed in FBGA (
μ
BGA
) package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 4bits prefetch-pipelined
architecture. Data strobe (DQS and /DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA
(
μ
BGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
Data rate: 533Mbps/400Mbps (max.)
SSTL_18 compatible I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Four internal banks for concurrent operation
(components)
Burst length: 4, 8
/CAS latency (CL): 3, 4, 5
Auto precharge option for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8
μ
s at 0
°
C
≤
TC
≤
+
85
°
C
3.9
μ
s at
+
85
°
C
<
TC
≤
+
95
°
C
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBE10RD4ABFA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank) |
| EBE10RD4ABFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank) |
| EBE10RD4AEFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank) |
| EBE10RD4AEFA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank) |
| EBE10RD4AEFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank) |
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